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Searched refs:PhysReg (Results 1 – 25 of 117) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRegMatrix.cpp88 const LiveInterval &VRegInterval, MCRegister PhysReg, in foreachUnit() argument
91 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in foreachUnit()
103 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in foreachUnit()
111 void LiveRegMatrix::assign(const LiveInterval &VirtReg, MCRegister PhysReg) { in assign() argument
113 << printReg(PhysReg, TRI) << ':'); in assign()
115 VRM->assignVirt2Phys(VirtReg.reg(), PhysReg); in assign()
118 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
129 Register PhysReg = VRM->getPhys(VirtReg.reg()); in unassign() local
131 << " from " << printReg(PhysReg, TRI) << ':'); in unassign()
134 foreachUnit(TRI, VirtReg, PhysReg, in unassign()
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H A DRegAllocFast.cpp203 MCPhysReg PhysReg = 0; ///< Currently held here. member
278 void setPhysRegState(MCRegister PhysReg, unsigned NewState);
279 bool isPhysRegFree(MCRegister PhysReg) const;
282 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr() argument
283 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in markRegUsedInInstr()
288 bool isClobberedByRegMasks(MCRegister PhysReg) const { in isClobberedByRegMasks()
289 return llvm::any_of(RegMasks, [PhysReg](const uint32_t *Mask) { in isClobberedByRegMasks()
290 return MachineOperand::clobbersPhysReg(Mask, PhysReg); in isClobberedByRegMasks()
295 bool isRegUsedInInstr(MCRegister PhysReg, bool LookAtPhysRegUses) const { in isRegUsedInInstr() argument
296 if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg)) in isRegUsedInInstr()
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H A DRegAllocGreedy.cpp535 MCRegister PhysReg; in tryAssign() local
536 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) { in tryAssign()
542 PhysReg = *I; in tryAssign()
545 if (!PhysReg.isValid()) in tryAssign()
546 return PhysReg; in tryAssign()
573 uint8_t Cost = RegCosts[PhysReg.id()]; in tryAssign()
577 return PhysReg; in tryAssign()
579 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " in tryAssign()
582 return CheapReg ? CheapReg : PhysReg; in tryAssign()
616 MCRegister PhysReg, in evictInterference() argument
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H A DRegAllocBasic.cpp118 bool spillInterferences(const LiveInterval &VirtReg, MCRegister PhysReg,
210 MCRegister PhysReg, in spillInterferences() argument
217 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in spillInterferences()
225 LLVM_DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI) in spillInterferences()
266 for (MCRegister PhysReg : Order) { in selectOrSplit() local
267 assert(PhysReg.isValid()); in selectOrSplit()
269 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit()
272 return PhysReg; in selectOrSplit()
276 PhysRegSpillCands.push_back(PhysReg); in selectOrSplit()
286 for (MCRegister &PhysReg : PhysRegSpillCands) { in selectOrSplit()
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H A DVirtRegMap.cpp216 void addLiveInsForSubRanges(const LiveInterval &LI, MCRegister PhysReg) const;
222 MCRegister PhysReg, const MachineInstr &MI) const;
365 MCRegister PhysReg) const { in addLiveInsForSubRanges()
404 MBB->addLiveIn(PhysReg, LaneMask); in addLiveInsForSubRanges()
420 MCRegister PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns() local
421 if (!PhysReg) { in addMBBLiveIns()
429 addLiveInsForSubRanges(LI, PhysReg); in addMBBLiveIns()
439 MBB->addLiveIn(PhysReg); in addMBBLiveIns()
610 MCRegister PhysReg, const MachineInstr &MI) const { in liveOutUndefPhiLanesForUndefSubregDef() argument
628 LRM->checkInterferenceLanes(BeforeMIUses, MIIndex.getRegSlot(), PhysReg); in liveOutUndefPhiLanesForUndefSubregDef()
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H A DRegisterClassInfo.cpp153 for (unsigned PhysReg : RawOrder) { in compute() local
155 if (Reserved.test(PhysReg)) in compute()
157 uint8_t Cost = RegCosts[PhysReg]; in compute()
160 if (getLastCalleeSavedAlias(PhysReg) && in compute()
161 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg)) in compute()
163 CSRAlias.push_back(PhysReg); in compute()
167 RCI.Order[N++] = PhysReg; in compute()
175 for (unsigned PhysReg : CSRAlias) { in compute() local
176 uint8_t Cost = RegCosts[PhysReg]; in compute()
179 RCI.Order[N++] = PhysReg; in compute()
H A DRegAllocEvictionAdvisor.cpp224 const LiveInterval &VirtReg, MCRegister PhysReg, in canEvictHintInterference() argument
228 return canEvictInterferenceBasedOnCost(VirtReg, PhysReg, true, MaxCost, in canEvictHintInterference()
242 const LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in canEvictInterferenceBasedOnCost() argument
245 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) in canEvictInterferenceBasedOnCost()
260 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in canEvictInterferenceBasedOnCost()
322 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) { in canEvictInterferenceBasedOnCost()
352 MCRegister PhysReg = *I; in tryFindEvictionCandidate() local
353 assert(PhysReg); in tryFindEvictionCandidate()
354 if (!canAllocatePhysReg(CostPerUseLimit, PhysReg) || in tryFindEvictionCandidate()
355 !canEvictInterferenceBasedOnCost(VirtReg, PhysReg, false, BestCost, in tryFindEvictionCandidate()
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H A DInterferenceCache.cpp62 InterferenceCache::Entry *InterferenceCache::get(MCRegister PhysReg) { in get() argument
63 unsigned char E = PhysRegEntries[PhysReg.id()]; in get()
64 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { in get()
80 Entries[E].reset(PhysReg, LIUArray, TRI, MF); in get()
81 PhysRegEntries[PhysReg.id()] = E; in get()
95 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in revalidate()
106 PhysReg = physReg; in reset()
112 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in reset()
121 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in valid()
192 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { in update()
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H A DInterferenceCache.h47 MCRegister PhysReg = 0; variable
105 PhysReg = MCRegister::NoRegister; in clear()
111 MCRegister getPhysReg() const { return PhysReg; } in getPhysReg()
155 Entry *get(MCRegister PhysReg);
209 void setPhysReg(InterferenceCache &Cache, MCRegister PhysReg) { in setPhysReg() argument
213 if (PhysReg.isValid()) in setPhysReg()
214 setEntry(Cache.get(PhysReg)); in setPhysReg()
H A DRegAllocGreedy.h230 MCRegister PhysReg; member
243 PhysReg = Reg; in reset()
327 bool mayRecolorAllInterferences(MCRegister PhysReg,
340 unsigned calculateRegionSplitCostAroundReg(MCPhysReg PhysReg,
361 AllocationOrder &Order, MCRegister PhysReg,
390 MCRegister PhysReg; member
392 HintInfo(BlockFrequency Freq, Register Reg, MCRegister PhysReg) in HintInfo()
393 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {} in HintInfo()
H A DMachineRegisterInfo.cpp532 bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { in isConstantPhysReg()
533 assert(PhysReg.isPhysical()); in isConstantPhysReg()
536 if (TRI->isConstantPhysReg(PhysReg)) in isConstantPhysReg()
541 for (MCRegAliasIterator AI(PhysReg, TRI, true); in isConstantPhysReg()
589 bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg, in isPhysRegModified() argument
591 if (UsedPhysRegMask.test(PhysReg.id())) in isPhysRegModified()
594 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) { in isPhysRegModified()
604 bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg, in isPhysRegUsed() argument
606 if (!SkipRegMaskTest && UsedPhysRegMask.test(PhysReg.id())) in isPhysRegUsed()
609 for (MCRegAliasIterator AliasReg(PhysReg, TRI, true); AliasReg.isValid(); in isPhysRegUsed()
H A DLiveRangeCalc.cpp86 void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, Register PhysReg, in extend() argument
104 if (findReachingDefs(LR, *UseMBB, Use, PhysReg, Undefs)) in extend()
191 SlotIndex Use, Register PhysReg, in findReachingDefs() argument
211 errs() << "Use of " << printReg(PhysReg, MRI->getTargetRegisterInfo()) in findReachingDefs()
219 if (PhysReg.isPhysical()) { in findReachingDefs()
221 bool IsLiveIn = MBB->isLiveIn(PhysReg); in findReachingDefs()
222 for (MCRegAliasIterator Alias(PhysReg, TRI, false); !IsLiveIn && Alias.isValid(); ++Alias) in findReachingDefs()
226 errs() << "The register " << printReg(PhysReg, TRI) in findReachingDefs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp109 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef() local
110 if (!MRI->isPhysRegUsed(PhysReg, /*SkipRegMaskTest=*/true) && in processDef()
111 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) { in processDef()
112 Matrix->assign(LI, PhysReg); in processDef()
113 assert(PhysReg != 0); in processDef()
136 Register PhysReg = VRM->getPhys(VirtReg); in rewriteRegs() local
139 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewriteRegs()
143 MO.setReg(PhysReg); in rewriteRegs()
154 const Register PhysReg = VRM->getPhys(Reg); in rewriteRegs() local
155 assert(PhysReg != 0); in rewriteRegs()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRegMatrix.h109 MCRegister PhysReg);
116 bool checkInterference(SlotIndex Start, SlotIndex End, MCRegister PhysReg);
126 MCRegister PhysReg);
131 void assign(const LiveInterval &VirtReg, MCRegister PhysReg);
139 bool isPhysRegUsed(MCRegister PhysReg) const;
152 MCRegister PhysReg = MCRegister::NoRegister);
158 MCRegister PhysReg);
170 Register getOneVReg(unsigned PhysReg) const;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp35 void assignValueToReg(Register ValVReg, Register PhysReg,
48 void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg() argument
50 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
52 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
143 Register PhysReg, in assignValueToReg() argument
145 markPhysRegUsed(PhysReg); in assignValueToReg()
146 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
181 void FormalArgHandler::markPhysRegUsed(unsigned PhysReg) { in markPhysRegUsed() argument
182 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
183 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
H A DPPCCallLowering.h47 void assignValueToReg(Register ValVReg, Register PhysReg,
58 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
63 void markPhysRegUsed(unsigned PhysReg) override;
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp41 void assignValueToReg(Register ValVReg, Register PhysReg,
59 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
61 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
63 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
150 Register PhysReg, in assignValueToReg() argument
152 MIRBuilder.getMRI()->addLiveIn(PhysReg); in assignValueToReg()
153 MIRBuilder.getMBB().addLiveIn(PhysReg); in assignValueToReg()
154 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
183 void CallReturnHandler::assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg() argument
185 MIB.addDef(PhysReg, RegState::Implicit); in assignValueToReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp119 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
122 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
128 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
129 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
292 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
295 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); in assignValueToReg()
303 markPhysRegUsed(PhysReg); in assignValueToReg()
305 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
312 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); in assignValueToReg()
357 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp
H A DX86RegisterInfo.cpp722 MCRegister PhysReg) const { in isFixedRegister()
727 if (TRI.isSuperOrSubRegisterEq(X86::RSP, PhysReg)) in isFixedRegister()
732 if (TFI.hasFP(MF) && TRI.isSuperOrSubRegisterEq(X86::RBP, PhysReg)) in isFixedRegister()
735 return X86GenRegisterInfo::isFixedRegister(MF, PhysReg); in isFixedRegister()
1180 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg)); in getRegAllocationHints() local
1181 if (PhysReg && !MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg)) in getRegAllocationHints()
1182 TwoAddrHints.insert(PhysReg); in getRegAllocationHints()
1214 auto AddHint = [&](MCPhysReg PhysReg) { in getRegAllocationHints() argument
1215 Register VReg = Matrix->getOneVReg(PhysReg); in getRegAllocationHints()
1217 Hints.push_back(PhysReg); in getRegAllocationHints()
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H A DX86TileConfig.cpp97 MCRegister PhysReg = VRM.getPhys(VirtReg); in collectVirtRegShapes() local
98 if (!PhysReg) in collectVirtRegShapes()
102 unsigned Index = PhysReg - X86::TMM0; in collectVirtRegShapes()
112 unsigned Index0 = (PhysReg - X86::TMM0_TMM1) * 2; in collectVirtRegShapes()
113 unsigned Index1 = (PhysReg - X86::TMM0_TMM1) * 2 + 1; in collectVirtRegShapes()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp108 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
110 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
112 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
219 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
221 markPhysRegUsed(PhysReg.asMCReg()); in assignValueToReg()
222 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
228 virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
238 void markPhysRegUsed(MCRegister PhysReg) override { in markPhysRegUsed()
239 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
240 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp95 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
98 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
99 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
108 Register PhysReg = VA.getLocReg(); in assignCustomValue() local
112 MIRBuilder.buildCopy(PhysReg, Trunc); in assignCustomValue()
113 MIB.addUse(PhysReg, RegState::Implicit); in assignCustomValue()
233 void assignValueToReg(Register ValVReg, Register PhysReg, in assignValueToReg()
235 markPhysRegUsed(PhysReg); in assignValueToReg()
236 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
245 Register PhysReg = VA.getLocReg(); in assignCustomValue() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp42 Register PhysReg = VRM->getPhys(MO.getReg()); in getRC32() local
43 if (SystemZ::GR32BitRegClass.contains(PhysReg)) in getRC32()
45 assert (SystemZ::GRH32BitRegClass.contains(PhysReg) && in getRC32()
109 Register PhysReg = in getRegAllocationHints() local
111 if (PhysReg) { in getRegAllocationHints()
113 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
115 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
117 if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg)) in getRegAllocationHints()
118 TwoAddrHints.insert(PhysReg); in getRegAllocationHints()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp95 void assignValueToReg(Register ValVReg, Register PhysReg,
109 virtual void markPhysRegUsed(unsigned PhysReg) { in markPhysRegUsed() argument
110 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
111 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
122 void markPhysRegUsed(unsigned PhysReg) override { in markPhysRegUsed() argument
123 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
132 Register PhysReg, in assignValueToReg() argument
134 markPhysRegUsed(PhysReg); in assignValueToReg()
135 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA); in assignValueToReg()
202 void assignValueToReg(Register ValVReg, Register PhysReg,
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