Lines Matching refs:PhysReg
203 MCPhysReg PhysReg = 0; ///< Currently held here. member
279 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
280 bool isPhysRegFree(MCPhysReg PhysReg) const;
283 void markRegUsedInInstr(MCPhysReg PhysReg) { in markRegUsedInInstr() argument
284 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in markRegUsedInInstr()
289 bool isClobberedByRegMasks(MCPhysReg PhysReg) const { in isClobberedByRegMasks()
290 return llvm::any_of(RegMasks, [PhysReg](const uint32_t *Mask) { in isClobberedByRegMasks()
291 return MachineOperand::clobbersPhysReg(Mask, PhysReg); in isClobberedByRegMasks()
296 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const { in isRegUsedInInstr() argument
297 if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg)) in isRegUsedInInstr()
299 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in isRegUsedInInstr()
307 void markPhysRegUsedInInstr(MCPhysReg PhysReg) { in markPhysRegUsedInInstr() argument
308 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in markPhysRegUsedInInstr()
315 void unmarkRegUsedInInstr(MCPhysReg PhysReg) { in unmarkRegUsedInInstr() argument
316 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in unmarkRegUsedInInstr()
344 bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
345 bool definePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
346 bool displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
347 void freePhysReg(MCPhysReg PhysReg);
349 unsigned calcSpillCost(MCPhysReg PhysReg) const;
359 void assignVirtToPhysReg(MachineInstr &MI, LiveReg &, MCPhysReg PhysReg);
376 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
386 MCPhysReg PhysReg);
449 void RegAllocFastImpl::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) { in setPhysRegState() argument
450 for (MCRegUnit Unit : TRI->regunits(PhysReg)) in setPhysRegState()
454 bool RegAllocFastImpl::isPhysRegFree(MCPhysReg PhysReg) const { in isPhysRegFree()
455 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in isPhysRegFree()
626 Register VirtReg, MCPhysReg PhysReg) { in reload() argument
628 << printReg(PhysReg, TRI) << '\n'); in reload()
631 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg); in reload()
671 MCPhysReg Reg = P.PhysReg; in reloadAtBegin()
684 MCPhysReg PhysReg = LR.PhysReg; in reloadAtBegin() local
685 if (PhysReg == 0) in reloadAtBegin()
688 MCRegister FirstUnit = *TRI->regunits(PhysReg).begin(); in reloadAtBegin()
695 if (PrologLiveIns.count(PhysReg)) { in reloadAtBegin()
699 reload(MBB.begin(), LR.VirtReg, PhysReg); in reloadAtBegin()
701 reload(InsertBefore, LR.VirtReg, PhysReg); in reloadAtBegin()
726 bool RegAllocFastImpl::displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) { in displacePhysReg() argument
729 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in displacePhysReg()
736 reload(ReloadBefore, VirtReg, LRI->PhysReg); in displacePhysReg()
738 setPhysRegState(LRI->PhysReg, regFree); in displacePhysReg()
739 LRI->PhysReg = 0; in displacePhysReg()
755 void RegAllocFastImpl::freePhysReg(MCPhysReg PhysReg) { in freePhysReg() argument
756 LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':'); in freePhysReg()
758 MCRegister FirstUnit = *TRI->regunits(PhysReg).begin(); in freePhysReg()
765 setPhysRegState(PhysReg, regFree); in freePhysReg()
771 setPhysRegState(LRI->PhysReg, regFree); in freePhysReg()
772 LRI->PhysReg = 0; in freePhysReg()
782 unsigned RegAllocFastImpl::calcSpillCost(MCPhysReg PhysReg) const { in calcSpillCost()
783 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in calcSpillCost()
789 << printReg(PhysReg, TRI) << '\n'); in calcSpillCost()
840 MCPhysReg PhysReg) { in assignVirtToPhysReg() argument
843 << printReg(PhysReg, TRI) << '\n'); in assignVirtToPhysReg()
844 assert(LR.PhysReg == 0 && "Already assigned a physreg"); in assignVirtToPhysReg()
845 assert(PhysReg != 0 && "Trying to assign no register"); in assignVirtToPhysReg()
846 LR.PhysReg = PhysReg; in assignVirtToPhysReg()
847 setPhysRegState(PhysReg, VirtReg); in assignVirtToPhysReg()
849 assignDanglingDebugValues(AtMI, VirtReg, PhysReg); in assignVirtToPhysReg()
894 assert(LR.PhysReg == 0); in allocVirtReg()
939 for (MCPhysReg PhysReg : AllocationOrder) { in allocVirtReg() local
940 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' '); in allocVirtReg()
941 if (isRegUsedInInstr(PhysReg, LookAtPhysRegUses)) { in allocVirtReg()
946 unsigned Cost = calcSpillCost(PhysReg); in allocVirtReg()
950 assignVirtToPhysReg(MI, LR, PhysReg); in allocVirtReg()
954 if (PhysReg == Hint0 || PhysReg == Hint1) in allocVirtReg()
958 BestReg = PhysReg; in allocVirtReg()
972 LR.PhysReg = 0; in allocVirtReg()
988 MCPhysReg PhysReg; in allocVirtRegUndef() local
989 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { in allocVirtRegUndef()
990 PhysReg = LRI->PhysReg; in allocVirtRegUndef()
995 PhysReg = AllocationOrder[0]; in allocVirtRegUndef()
1000 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
1003 MO.setReg(PhysReg); in allocVirtRegUndef()
1017 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg()
1022 LRI->PhysReg = 0; in defineLiveThroughVirtReg()
1026 LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to " in defineLiveThroughVirtReg()
1030 .addReg(LRI->PhysReg, llvm::RegState::Kill); in defineLiveThroughVirtReg()
1066 if (LRI->PhysReg == 0) { in defineVirtReg()
1078 assert(!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) && in defineVirtReg()
1082 << printReg(LRI->PhysReg, TRI) << '\n'); in defineVirtReg()
1085 MCPhysReg PhysReg = LRI->PhysReg; in defineVirtReg() local
1093 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut); in defineVirtReg()
1103 TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill, FI, in defineVirtReg()
1106 Succ->addLiveIn(PhysReg); in defineVirtReg()
1117 BundleVirtRegsMap[VirtReg] = PhysReg; in defineVirtReg()
1119 markRegUsedInInstr(PhysReg); in defineVirtReg()
1120 return setPhysReg(MI, MO, PhysReg); in defineVirtReg()
1147 if (LRI->PhysReg == 0) { in useVirtReg()
1173 BundleVirtRegsMap[VirtReg] = LRI->PhysReg; in useVirtReg()
1175 markRegUsedInInstr(LRI->PhysReg); in useVirtReg()
1176 return setPhysReg(MI, MO, LRI->PhysReg); in useVirtReg()
1182 MCPhysReg PhysReg) { in setPhysReg() argument
1184 MO.setReg(PhysReg); in setPhysReg()
1190 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); in setPhysReg()
1201 MI.addRegisterKilled(PhysReg, TRI, true); in setPhysReg()
1210 MI.addRegisterDead(PhysReg, TRI, true); in setPhysReg()
1212 MI.addRegisterDefined(PhysReg, TRI); in setPhysReg()
1244 assert(TRI->hasRegUnit(I->PhysReg, Unit) && "inverse mapping present"); in dumpState()
1254 MCPhysReg PhysReg = LR.PhysReg; in dumpState() local
1255 if (PhysReg != 0) { in dumpState()
1256 assert(Register::isPhysicalRegister(PhysReg) && "mapped to physreg"); in dumpState()
1257 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { in dumpState()
1544 MCPhysReg PhysReg = LR.PhysReg; in allocateInstruction() local
1545 if (PhysReg != 0 && isClobberedByRegMasks(PhysReg)) in allocateInstruction()
1546 displacePhysReg(MI, PhysReg); in allocateInstruction()
1676 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) { in handleDebugValue()
1679 setPhysReg(MI, *RegMO, LRI->PhysReg); in handleDebugValue()
1722 setPhysRegState(LiveReg.PhysReg, regPreAssigned); in allocateBasicBlock()