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Searched refs:Opcode (Results 1 – 25 of 692) sorted by relevance

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/freebsd/contrib/llvm-project/lldb/include/lldb/Core/
H A DOpcode.h29 class Opcode {
41 Opcode() = default;
43 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
48 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
53 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
58 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
63 Opcode(uint8_t *bytes, size_t length) in Opcode() function
70 m_type = Opcode::eTypeInvalid; in Clear()
73 Opcode::Type GetType() const { return m_type; } in GetType()
77 case Opcode::eTypeInvalid:
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h104 static BranchPredicate getBranchPredicate(unsigned Opcode);
133 unsigned Opcode) const;
136 unsigned Opcode) const;
139 unsigned Opcode, bool Swap = false) const;
142 unsigned Opcode,
158 unsigned Opcode,
412 bool isSALU(uint16_t Opcode) const { in isSALU() argument
413 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
420 bool isVALU(uint16_t Opcode) const { in isVALU() argument
421 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
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H A DR600InstrInfo.h84 bool isALUInstr(unsigned Opcode) const;
85 bool hasInstrModifiers(unsigned Opcode) const;
86 bool isLDSInstr(unsigned Opcode) const;
87 bool isLDSRetInstr(unsigned Opcode) const;
93 bool isTransOnly(unsigned Opcode) const;
95 bool isVectorOnly(unsigned Opcode) const;
97 bool isExport(unsigned Opcode) const;
99 bool usesVertexCache(unsigned Opcode) const;
101 bool usesTextureCache(unsigned Opcode) const;
104 bool mustBeLastInClause(unsigned Opcode) const;
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp63 bool isLoadInst(unsigned Opcode);
77 unsigned Opcode);
97 static bool isST(unsigned Opcode) { in isST() argument
98 return Opcode == BPF::STB_imm || Opcode == BPF::STH_imm || in isST()
99 Opcode == BPF::STW_imm || Opcode == BPF::STD_imm; in isST()
102 static bool isSTX32(unsigned Opcode) { in isSTX32() argument
103 return Opcode == BPF::STB32 || Opcode == BPF::STH32 || Opcode == BPF::STW32; in isSTX32()
106 static bool isSTX64(unsigned Opcode) { in isSTX64() argument
107 return Opcode == BPF::STB || Opcode == BPF::STH || Opcode == BPF::STW || in isSTX64()
108 Opcode == BPF::STD; in isSTX64()
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/freebsd/contrib/llvm-project/clang/lib/AST/Interp/
H A DOpcodes.td1 //===--- Opcodes.td - Opcode defitions for the constexpr VM -----*- C++ -*-===//
129 class Opcode {
140 class AluOpcode : Opcode {
145 class FloatOpcode : Opcode {
149 class IntegerOpcode : Opcode {
158 class JumpOpcode : Opcode {
176 def Ret : Opcode {
184 def RetVoid : Opcode {
190 def RetValue : Opcode {
196 def NoRet : Opcode {}
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/freebsd/contrib/llvm-project/lldb/source/Core/
H A DOpcode.cpp24 int Opcode::Dump(Stream *s, uint32_t min_byte_width) { in Dump()
27 case Opcode::eTypeInvalid: in Dump()
30 case Opcode::eType8: in Dump()
33 case Opcode::eType16: in Dump()
36 case Opcode::eType16_2: in Dump()
37 case Opcode::eType32: in Dump()
41 case Opcode::eType64: in Dump()
45 case Opcode::eTypeBytes: in Dump()
62 lldb::ByteOrder Opcode::GetDataByteOrder() const { in GetDataByteOrder()
67 case Opcode::eTypeInvalid: in GetDataByteOrder()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp169 getEEWAndEMUL(unsigned Opcode, RISCVII::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL() argument
171 switch (Opcode) { in getEEWAndEMUL()
208 bool opcodeHasEEWAndEMULInfo(unsigned short Opcode) { in opcodeHasEEWAndEMULInfo() argument
209 return Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V || in opcodeHasEEWAndEMULInfo()
210 Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V || in opcodeHasEEWAndEMULInfo()
211 Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V || in opcodeHasEEWAndEMULInfo()
212 Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V || in opcodeHasEEWAndEMULInfo()
213 Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V || in opcodeHasEEWAndEMULInfo()
214 Opcode == RISCV::VLSE8_V || Opcode == RISCV::VSSE8_V || in opcodeHasEEWAndEMULInfo()
215 Opcode == RISCV::VLSE16_V || Opcode == RISCV::VSSE16_V || in opcodeHasEEWAndEMULInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPostLegalizer.cpp44 extern bool isTypeFoldingSupported(unsigned Opcode);
56 static bool isMetaInstrGET(unsigned Opcode) { in isMetaInstrGET() argument
57 return Opcode == SPIRV::GET_ID || Opcode == SPIRV::GET_ID64 || in isMetaInstrGET()
58 Opcode == SPIRV::GET_fID || Opcode == SPIRV::GET_fID64 || in isMetaInstrGET()
59 Opcode == SPIRV::GET_pID32 || Opcode == SPIRV::GET_pID64 || in isMetaInstrGET()
60 Opcode == SPIRV::GET_vID || Opcode == SPIRV::GET_vfID || in isMetaInstrGET()
61 Opcode == SPIRV::GET_vpID32 || Opcode == SPIRV::GET_vpID64; in isMetaInstrGET()
64 static bool mayBeInserted(unsigned Opcode) { in mayBeInserted() argument
65 switch (Opcode) { in mayBeInserted()
76 return isTypeFoldingSupported(Opcode); in mayBeInserted()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetTransformInfo.cpp107 InstructionCost SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument
122 switch (Opcode) { in getIntImmCostInst()
426 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost() argument
433 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, in getArithmeticInstrCost()
453 Opcode == Instruction::SDiv || Opcode == Instruction::SRem; in getArithmeticInstrCost()
455 Opcode == Instruction::UDiv || Opcode == Instruction::URem; in getArithmeticInstrCost()
478 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub || in getArithmeticInstrCost()
479 Opcode == Instruction::FMul || Opcode == Instruction::FDiv) in getArithmeticInstrCost()
483 if (Opcode == Instruction::FRem) in getArithmeticInstrCost()
488 if (Opcode == Instruction::Xor) { in getArithmeticInstrCost()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstruction.h290 static const char *getOpcodeName(unsigned Opcode);
292 static inline bool isTerminator(unsigned Opcode) {
293 return Opcode >= TermOpsBegin && Opcode < TermOpsEnd;
296 static inline bool isUnaryOp(unsigned Opcode) {
297 return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd;
299 static inline bool isBinaryOp(unsigned Opcode) {
300 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd;
303 static inline bool isIntDivRem(unsigned Opcode) {
304 return Opcode == UDiv || Opcode == SDiv || Opcode == URem || Opcode == SRem;
308 static inline bool isShift(unsigned Opcode) {
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp133 static bool isXMMLoadOpcode(unsigned Opcode) { in isXMMLoadOpcode() argument
134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
137 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
138 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm || in isXMMLoadOpcode()
139 Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm || in isXMMLoadOpcode()
140 Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm || in isXMMLoadOpcode()
141 Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm; in isXMMLoadOpcode()
143 static bool isYMMLoadOpcode(unsigned Opcode) { in isYMMLoadOpcode() argument
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanPatternMatch.h112 template <unsigned Opcode, typename...> struct MatchRecipeAndOpcode {};
114 template <unsigned Opcode, typename RecipeTy>
115 struct MatchRecipeAndOpcode<Opcode, RecipeTy> {
118 return DefR && DefR->getOpcode() == Opcode;
122 template <unsigned Opcode, typename RecipeTy, typename... RecipeTys>
123 struct MatchRecipeAndOpcode<Opcode, RecipeTy, RecipeTys...> {
125 return MatchRecipeAndOpcode<Opcode, RecipeTy>::match(R) ||
126 MatchRecipeAndOpcode<Opcode, RecipeTys...>::match(R);
131 template <typename Op0_t, unsigned Opcode, typename... RecipeTys>
143 if (!detail::MatchRecipeAndOpcode<Opcode, RecipeTys...>::match(R))
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/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp112 static Desc getDescImpl(ArrayRef<Desc> Descriptions, unsigned Opcode) { in getDescImpl() argument
114 if (Opcode >= Descriptions.size()) in getDescImpl()
116 return Descriptions[Opcode]; in getDescImpl()
119 static Desc getOpDesc(unsigned Opcode) { in getOpDesc() argument
121 return getDescImpl(Descriptions, Opcode); in getOpDesc()
135 static Desc getSubOpDesc(unsigned Opcode, unsigned SubOpcode) { in getSubOpDesc() argument
136 assert(Opcode == DW_OP_LLVM_user); in getSubOpDesc()
145 Opcode = Data.getU8(&Offset); in extract()
147 Desc = getOpDesc(Opcode); in extract()
161 Desc = getSubOpDesc(Opcode, Operands[Operand]); in extract()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegacyLegalizerInfo.h85 unsigned Opcode; member
89 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {} in InstrAspect()
90 InstrAspect(unsigned Opcode, unsigned Idx, LLT Type) in InstrAspect()
91 : Opcode(Opcode), Idx(Idx), Type(Type) {} in InstrAspect()
94 return Opcode == RHS.Opcode && Idx == RHS.Idx && Type == RHS.Type;
158 const unsigned OpcodeIdx = Aspect.Opcode - FirstOp; in setAction()
180 void setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeScalarToDifferentSizeStrategy() argument
183 const unsigned OpcodeIdx = Opcode - FirstOp; in setLegalizeScalarToDifferentSizeStrategy()
191 void setLegalizeVectorElementToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeVectorElementToDifferentSizeStrategy() argument
194 const unsigned OpcodeIdx = Opcode - FirstOp; in setLegalizeVectorElementToDifferentSizeStrategy()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetOpcodes.h30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode() argument
31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode() argument
37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint() argument
43 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START && in isPreISelGenericOptimizationHint()
44 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END; in isPreISelGenericOptimizationHint()
H A DISDOpcodes.h1466 inline bool isBitwiseLogicOp(unsigned Opcode) { in isBitwiseLogicOp() argument
1467 return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR; in isBitwiseLogicOp()
1475 bool isVPOpcode(unsigned Opcode);
1478 bool isVPBinaryOp(unsigned Opcode);
1481 bool isVPReduction(unsigned Opcode);
1484 std::optional<unsigned> getVPMaskIdx(unsigned Opcode);
1487 std::optional<unsigned> getVPExplicitVectorLengthIdx(unsigned Opcode);
1490 std::optional<unsigned> getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept);
1493 unsigned getVPForBaseOpcode(unsigned Opcode);
1645 inline bool isExtOpcode(unsigned Opcode) { in isExtOpcode() argument
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerInfo.cpp80 OS << "Opcode=" << Opcode << ", Tys={"; in print()
269 unsigned LegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const { in getOpcodeIdxForOpcode()
270 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode"); in getOpcodeIdxForOpcode()
271 return Opcode - FirstOp; in getOpcodeIdxForOpcode()
274 unsigned LegalizerInfo::getActionDefinitionsIdx(unsigned Opcode) const { in getActionDefinitionsIdx()
275 unsigned OpcodeIdx = getOpcodeIdxForOpcode(Opcode); in getActionDefinitionsIdx()
277 LLVM_DEBUG(dbgs() << ".. opcode " << Opcode << " is aliased to " << Alias in getActionDefinitionsIdx()
287 LegalizerInfo::getActionDefinitions(unsigned Opcode) const { in getActionDefinitions()
288 unsigned OpcodeIdx = getActionDefinitionsIdx(Opcode); in getActionDefinitions()
292 LegalizeRuleSet &LegalizerInfo::getActionDefinitionsBuilder(unsigned Opcode) { in getActionDefinitionsBuilder() argument
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DMatchContext.h32 bool match(SDValue OpN, unsigned Opcode) const { in match() argument
33 return Opcode == OpN->getOpcode(); in match()
74 std::optional<unsigned> Opcode = ISD::getBaseOpcodeForVP( in getRootBaseOpcode() local
76 assert(Opcode.has_value()); in getRootBaseOpcode()
77 return *Opcode; in getRootBaseOpcode()
111 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { in getNode() argument
112 unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); in getNode()
119 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
121 unsigned VPOpcode = ISD::getVPForBaseOpcode(Opcode); in getNode()
127 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
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/freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/
H A DARMEHABIPrinter.h99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
100 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode, in Decode_00xxxxxx()
101 ((Opcode & 0x3f) << 2) + 4); in Decode_00xxxxxx()
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
106 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode, in Decode_01xxxxxx()
107 ((Opcode & 0x3f) << 2) + 4); in Decode_01xxxxxx()
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
125 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode); in Decode_10011101()
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
130 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode); in Decode_10011111()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonTargetTransformInfo.cpp164 InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, in getMemoryOpCost() argument
170 assert(Opcode == Instruction::Load || Opcode == Instruction::Store); in getMemoryOpCost()
175 if (Opcode == Instruction::Store) in getMemoryOpCost()
176 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getMemoryOpCost()
217 return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind, in getMemoryOpCost()
222 HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, in getMaskedMemoryOpCost() argument
225 return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, in getMaskedMemoryOpCost()
239 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, in getGatherScatterOpCost() argument
241 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, in getGatherScatterOpCost()
246 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, in getInterleavedMemoryOpCost() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMakeCompressible.cpp98 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth() argument
99 switch (Opcode) { in log2LdstWidth()
123 static unsigned offsetMask(unsigned Opcode) { in offsetMask() argument
124 switch (Opcode) { in offsetMask()
148 static uint8_t compressedLDSTOffsetMask(unsigned Opcode) { in compressedLDSTOffsetMask() argument
149 return offsetMask(Opcode) << log2LdstWidth(Opcode); in compressedLDSTOffsetMask()
154 static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) { in compressibleSPOffset() argument
156 switch (log2LdstWidth(Opcode)) { in compressibleSPOffset()
168 static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) { in getBaseAdjustForCompression() argument
170 return Offset & ~compressedLDSTOffsetMask(Opcode); in getBaseAdjustForCompression()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.h72 void EmitInt8(unsigned Opcode) { in EmitInt8() argument
73 Ops.push_back(Opcode & 0xff); in EmitInt8()
77 void EmitInt16(unsigned Opcode) { in EmitInt16() argument
78 Ops.push_back((Opcode >> 8) & 0xff); in EmitInt16()
79 Ops.push_back(Opcode & 0xff); in EmitInt16()
83 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes() argument
84 Ops.insert(Ops.end(), Opcode, Opcode + Size); in emitBytes()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp190 static unsigned getOppositeBranchOpc(unsigned Opcode) { in getOppositeBranchOpc() argument
191 switch (Opcode) { in getOppositeBranchOpc()
405 unsigned Opcode = 0; in storeRegToStackSlot() local
408 Opcode = CSKY::ST32W; // Optimize for 16bit in storeRegToStackSlot()
410 Opcode = CSKY::SPILL_CARRY; in storeRegToStackSlot()
413 Opcode = CSKY::FST_S; in storeRegToStackSlot()
415 Opcode = CSKY::FST_D; in storeRegToStackSlot()
417 Opcode = CSKY::f2FST_S; in storeRegToStackSlot()
419 Opcode = CSKY::f2FST_D; in storeRegToStackSlot()
428 BuildMI(MBB, I, DL, get(Opcode)) in storeRegToStackSlot()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp178 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
184 int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
221 unsigned Opcode = MI.getOpcode(); in getMemoryOpOffset() local
222 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
226 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
227 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
228 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
229 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
233 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
234 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp230 InstructionCost PPCTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument
235 return BaseT::getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst); in getIntImmCostInst()
246 switch (Opcode) { in getIntImmCostInst()
553 InstructionCost PPCTTIImpl::vectorCostAdjustmentFactor(unsigned Opcode, in vectorCostAdjustmentFactor() argument
571 int ISD = TLI->InstructionOpcodeToISD(Opcode); in vectorCostAdjustmentFactor()
585 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost() argument
589 assert(TLI->InstructionOpcodeToISD(Opcode) && "Invalid opcode"); in getArithmeticInstrCost()
591 InstructionCost CostFactor = vectorCostAdjustmentFactor(Opcode, Ty, nullptr); in getArithmeticInstrCost()
597 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, in getArithmeticInstrCost()
602 Opcode, Ty, CostKind, Op1Info, Op2Info); in getArithmeticInstrCost()
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