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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/SandboxVectorizer/
H A DLegality.cpp36 auto Opcode = I0->getOpcode(); in notVectorizableBasedOnOpcodesAndTypes() local
38 if (any_of(drop_begin(Bndl), [Opcode](Value *V) { in notVectorizableBasedOnOpcodesAndTypes()
39 return cast<Instruction>(V)->getOpcode() != Opcode; in notVectorizableBasedOnOpcodesAndTypes()
78 switch (Opcode) { in notVectorizableBasedOnOpcodesAndTypes()
79 case Instruction::Opcode::ZExt: in notVectorizableBasedOnOpcodesAndTypes()
80 case Instruction::Opcode::SExt: in notVectorizableBasedOnOpcodesAndTypes()
81 case Instruction::Opcode::FPToUI: in notVectorizableBasedOnOpcodesAndTypes()
82 case Instruction::Opcode::FPToSI: in notVectorizableBasedOnOpcodesAndTypes()
83 case Instruction::Opcode::FPExt: in notVectorizableBasedOnOpcodesAndTypes()
84 case Instruction::Opcode::PtrToInt: in notVectorizableBasedOnOpcodesAndTypes()
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/freebsd/contrib/llvm-project/lldb/include/lldb/Core/
H A DOpcode.h29 class Opcode {
44 Opcode() = default;
46 Opcode(uint8_t inst, lldb::ByteOrder order) in Opcode() function
51 Opcode(uint16_t inst, lldb::ByteOrder order) in Opcode() function
56 Opcode(uint32_t inst, lldb::ByteOrder order) in Opcode() function
61 Opcode(uint64_t inst, lldb::ByteOrder order) in Opcode() function
66 Opcode(uint8_t *bytes, size_t length, Opcode::Type type, in Opcode() function
73 m_type = Opcode::eTypeInvalid; in Clear()
76 Opcode::Type GetType() const { return m_type; } in GetType()
80 case Opcode::eTypeInvalid:
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp61 bool isLoadInst(unsigned Opcode);
75 unsigned Opcode);
95 static bool isStoreImm(unsigned Opcode) { in isStoreImm() argument
96 return Opcode == BPF::STB_imm || Opcode == BPF::STH_imm || in isStoreImm()
97 Opcode == BPF::STW_imm || Opcode == BPF::STD_imm; in isStoreImm()
100 static bool isStore32(unsigned Opcode) { in isStore32() argument
101 return Opcode == BPF::STB32 || Opcode == BPF::STH32 || Opcode == BPF::STW32 || in isStore32()
102 Opcode == BPF::STBREL32 || Opcode == BPF::STHREL32 || in isStore32()
103 Opcode == BPF::STWREL32; in isStore32()
106 static bool isStore64(unsigned Opcode) { in isStore64() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h106 static BranchPredicate getBranchPredicate(unsigned Opcode);
135 unsigned Opcode) const;
138 unsigned Opcode) const;
141 unsigned Opcode, bool Swap = false) const;
144 unsigned Opcode,
160 unsigned Opcode,
431 bool isSALU(uint16_t Opcode) const { in isSALU() argument
432 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
439 bool isVALU(uint16_t Opcode) const { in isVALU() argument
440 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
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/freebsd/contrib/llvm-project/clang/lib/AST/ByteCode/
H A DOpcodes.td1 //===--- Opcodes.td - Opcode defitions for the constexpr VM -----*- C++ -*-===//
138 class Opcode {
149 class AluOpcode : Opcode {
154 class FloatOpcode : Opcode {
158 class IntegerOpcode : Opcode {
167 class JumpOpcode : Opcode {
180 def StartSpeculation : Opcode;
181 def EndSpeculation : Opcode;
182 def BCP : Opcode {
193 def Ret : Opcode {
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/freebsd/contrib/llvm-project/lldb/source/Core/
H A DOpcode.cpp24 int Opcode::Dump(Stream *s, uint32_t min_byte_width) const { in Dump()
27 case Opcode::eTypeInvalid: in Dump()
30 case Opcode::eType8: in Dump()
33 case Opcode::eType16: in Dump()
36 case Opcode::eType16_2: in Dump()
37 case Opcode::eType32: in Dump()
41 case Opcode::eType16_32Tuples: { in Dump()
62 case Opcode::eType64: in Dump()
66 case Opcode::eTypeBytes: in Dump()
83 lldb::ByteOrder Opcode::GetDataByteOrder() const { in GetDataByteOrder()
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/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/LowLevel/
H A DDWARFCFIProgram.h43 Instruction(uint8_t Opcode) : Opcode(Opcode) {} in Instruction()
45 uint8_t Opcode; member
90 uint8_t Opcode = Data.getRelocatedValue(C, 1); in parse() local
95 if (uint8_t Primary = Opcode & DWARF_CFI_PRIMARY_OPCODE_MASK) { in parse()
98 uint64_t Op1 = Opcode & DWARF_CFI_PRIMARY_OPERAND_MASK; in parse()
114 switch (Opcode) { in parse()
118 Opcode); in parse()
125 addInstruction(Opcode); in parse()
129 addInstruction(Opcode, Data.getRelocatedAddress(C)); in parse()
133 addInstruction(Opcode, Data.getRelocatedValue(C, 1)); in parse()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/
H A DBottomUpVec.cpp81 auto Opcode = cast<Instruction>(Bndl[0])->getOpcode(); in createVectorInstr() local
82 switch (Opcode) { in createVectorInstr()
83 case Instruction::Opcode::ZExt: in createVectorInstr()
84 case Instruction::Opcode::SExt: in createVectorInstr()
85 case Instruction::Opcode::FPToUI: in createVectorInstr()
86 case Instruction::Opcode::FPToSI: in createVectorInstr()
87 case Instruction::Opcode::FPExt: in createVectorInstr()
88 case Instruction::Opcode::PtrToInt: in createVectorInstr()
89 case Instruction::Opcode::IntToPtr: in createVectorInstr()
90 case Instruction::Opcode::SIToFP: in createVectorInstr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCA/
H A DRISCVCustomBehaviour.cpp183 getEEWAndEMUL(unsigned Opcode, RISCVVType::VLMUL LMUL, uint8_t SEW) { in getEEWAndEMUL() argument
185 switch (Opcode) { in getEEWAndEMUL()
222 static bool opcodeHasEEWAndEMULInfo(unsigned short Opcode) { in opcodeHasEEWAndEMULInfo() argument
223 return Opcode == RISCV::VLM_V || Opcode == RISCV::VSM_V || in opcodeHasEEWAndEMULInfo()
224 Opcode == RISCV::VLE8_V || Opcode == RISCV::VSE8_V || in opcodeHasEEWAndEMULInfo()
225 Opcode == RISCV::VLE16_V || Opcode == RISCV::VSE16_V || in opcodeHasEEWAndEMULInfo()
226 Opcode == RISCV::VLE32_V || Opcode == RISCV::VSE32_V || in opcodeHasEEWAndEMULInfo()
227 Opcode == RISCV::VLE64_V || Opcode == RISCV::VSE64_V || in opcodeHasEEWAndEMULInfo()
228 Opcode == RISCV::VLSE8_V || Opcode == RISCV::VSSE8_V || in opcodeHasEEWAndEMULInfo()
229 Opcode == RISCV::VLSE16_V || Opcode == RISCV::VSSE16_V || in opcodeHasEEWAndEMULInfo()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstruction.h329 LLVM_ABI static const char *getOpcodeName(unsigned Opcode);
331 static inline bool isTerminator(unsigned Opcode) {
332 return Opcode >= TermOpsBegin && Opcode < TermOpsEnd;
335 static inline bool isUnaryOp(unsigned Opcode) {
336 return Opcode >= UnaryOpsBegin && Opcode < UnaryOpsEnd;
338 static inline bool isBinaryOp(unsigned Opcode) {
339 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd;
342 static inline bool isIntDivRem(unsigned Opcode) {
343 return Opcode == UDiv || Opcode == SDiv || Opcode == URem || Opcode == SRem;
346 static inline bool isFPDivRem(unsigned Opcode) {
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp132 static bool isXMMLoadOpcode(unsigned Opcode) { in isXMMLoadOpcode() argument
133 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm || in isXMMLoadOpcode()
134 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm || in isXMMLoadOpcode()
135 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm || in isXMMLoadOpcode()
136 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm || in isXMMLoadOpcode()
137 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm || in isXMMLoadOpcode()
138 Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm || in isXMMLoadOpcode()
139 Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm || in isXMMLoadOpcode()
140 Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm; in isXMMLoadOpcode()
142 static bool isYMMLoadOpcode(unsigned Opcode) { in isYMMLoadOpcode() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetTransformInfo.cpp186 InstructionCost SystemZTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, in getIntImmCostInst() argument
201 switch (Opcode) { in getIntImmCostInst()
543 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost() argument
549 return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, in getArithmeticInstrCost()
569 Opcode == Instruction::SDiv || Opcode == Instruction::SRem; in getArithmeticInstrCost()
571 Opcode == Instruction::UDiv || Opcode == Instruction::URem; in getArithmeticInstrCost()
594 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub || in getArithmeticInstrCost()
595 Opcode == Instruction::FMul || Opcode == Instruction::FDiv) in getArithmeticInstrCost()
599 if (Opcode == Instruction::FRem) in getArithmeticInstrCost()
604 if (Opcode == Instruction::Xor) { in getArithmeticInstrCost()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegacyLegalizerInfo.h86 unsigned Opcode; member
90 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Type(Type) {} in InstrAspect()
91 InstrAspect(unsigned Opcode, unsigned Idx, LLT Type) in InstrAspect()
92 : Opcode(Opcode), Idx(Idx), Type(Type) {} in InstrAspect()
95 return Opcode == RHS.Opcode && Idx == RHS.Idx && Type == RHS.Type;
159 const unsigned OpcodeIdx = Aspect.Opcode - FirstOp; in setAction()
181 void setLegalizeScalarToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeScalarToDifferentSizeStrategy() argument
184 const unsigned OpcodeIdx = Opcode - FirstOp; in setLegalizeScalarToDifferentSizeStrategy()
192 void setLegalizeVectorElementToDifferentSizeStrategy(const unsigned Opcode, in setLegalizeVectorElementToDifferentSizeStrategy() argument
195 const unsigned OpcodeIdx = Opcode - FirstOp; in setLegalizeVectorElementToDifferentSizeStrategy()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetOpcodes.h30 inline bool isPreISelGenericOpcode(unsigned Opcode) { in isPreISelGenericOpcode() argument
31 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START && in isPreISelGenericOpcode()
32 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isPreISelGenericOpcode()
36 inline bool isTargetSpecificOpcode(unsigned Opcode) { in isTargetSpecificOpcode() argument
37 return Opcode > TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END; in isTargetSpecificOpcode()
42 inline bool isPreISelGenericOptimizationHint(unsigned Opcode) { in isPreISelGenericOptimizationHint() argument
43 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_START && in isPreISelGenericOptimizationHint()
44 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPTIMIZATION_HINT_END; in isPreISelGenericOptimizationHint()
H A DSDNodeInfo.h89 bool hasDesc(unsigned Opcode) const { in hasDesc() argument
90 assert(Opcode >= ISD::BUILTIN_OP_END && "Expected target-specific opcode"); in hasDesc()
91 return Opcode < ISD::BUILTIN_OP_END + NumOpcodes; in hasDesc()
95 const SDNodeDesc &getDesc(unsigned Opcode) const { in getDesc() argument
96 assert(hasDesc(Opcode)); in getDesc()
97 return Descs[Opcode - ISD::BUILTIN_OP_END]; in getDesc()
101 ArrayRef<SDTypeConstraint> getConstraints(unsigned Opcode) const { in getConstraints() argument
102 const SDNodeDesc &Desc = getDesc(Opcode); in getConstraints()
108 StringRef getName(unsigned Opcode) const { in getName() argument
109 return Names[getDesc(Opcode).NameOffset]; in getName()
H A DSelectionDAGTargetInfo.h41 virtual const char *getTargetNodeName(unsigned Opcode) const { in getTargetNodeName() argument
48 virtual bool isTargetMemoryOpcode(unsigned Opcode) const { return false; } in isTargetMemoryOpcode() argument
52 virtual bool isTargetStrictFPOpcode(unsigned Opcode) const { return false; } in isTargetStrictFPOpcode() argument
56 virtual bool mayRaiseFPException(unsigned Opcode) const;
202 const char *getTargetNodeName(unsigned Opcode) const override { in getTargetNodeName() argument
203 assert(GenNodeInfo.hasDesc(Opcode) && in getTargetNodeName()
205 return GenNodeInfo.getName(Opcode).data(); in getTargetNodeName()
208 bool isTargetMemoryOpcode(unsigned Opcode) const override { in isTargetMemoryOpcode() argument
209 if (GenNodeInfo.hasDesc(Opcode)) in isTargetMemoryOpcode()
210 return GenNodeInfo.getDesc(Opcode).hasProperty(SDNPMemOperand); in isTargetMemoryOpcode()
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H A DISDOpcodes.h1572 inline bool isBitwiseLogicOp(unsigned Opcode) { in isBitwiseLogicOp() argument
1573 return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR; in isBitwiseLogicOp()
1585 LLVM_ABI bool isVPOpcode(unsigned Opcode);
1588 LLVM_ABI bool isVPBinaryOp(unsigned Opcode);
1591 LLVM_ABI bool isVPReduction(unsigned Opcode);
1594 LLVM_ABI std::optional<unsigned> getVPMaskIdx(unsigned Opcode);
1597 LLVM_ABI std::optional<unsigned> getVPExplicitVectorLengthIdx(unsigned Opcode);
1600 LLVM_ABI std::optional<unsigned> getBaseOpcodeForVP(unsigned Opcode,
1604 LLVM_ABI std::optional<unsigned> getVPForBaseOpcode(unsigned Opcode);
1756 inline bool isExtOpcode(unsigned Opcode) { in isExtOpcode() argument
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanPatternMatch.h198 template <typename Ops_t, unsigned Opcode, bool Commutative,
225 assert(Opcode == VPInstruction::BuildVector && in match()
262 return DefR && DefR->getOpcode() == Opcode; in matchRecipeAndOpcode()
273 template <unsigned Opcode, typename... RecipeTys>
275 Recipe_match<std::tuple<>, Opcode, false, RecipeTys...>;
277 template <typename Op0_t, unsigned Opcode, typename... RecipeTys>
279 Recipe_match<std::tuple<Op0_t>, Opcode, false, RecipeTys...>;
281 template <typename Op0_t, unsigned Opcode>
283 UnaryRecipe_match<Op0_t, Opcode, VPInstruction>;
285 template <unsigned Opcode>
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerInfo.cpp86 OS << "Opcode=" << Opcode << ", Tys={"; in print()
289 unsigned LegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const { in getOpcodeIdxForOpcode()
290 assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode"); in getOpcodeIdxForOpcode()
291 return Opcode - FirstOp; in getOpcodeIdxForOpcode()
294 unsigned LegalizerInfo::getActionDefinitionsIdx(unsigned Opcode) const { in getActionDefinitionsIdx()
295 unsigned OpcodeIdx = getOpcodeIdxForOpcode(Opcode); in getActionDefinitionsIdx()
298 LLVM_DEBUG(dbgs() << ".. opcode " << Opcode << " is aliased to " << Alias in getActionDefinitionsIdx()
309 LegalizerInfo::getActionDefinitions(unsigned Opcode) const { in getActionDefinitions()
310 unsigned OpcodeIdx = getActionDefinitionsIdx(Opcode); in getActionDefinitions()
314 LegalizeRuleSet &LegalizerInfo::getActionDefinitionsBuilder(unsigned Opcode) { in getActionDefinitionsBuilder() argument
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/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpressionPrinter.cpp172 uint8_t Opcode = Op.getCode(); in printCompactDWARFExpr() local
173 switch (Opcode) { in printCompactDWARFExpr()
226 if (Opcode >= dwarf::DW_OP_reg0 && Opcode <= dwarf::DW_OP_reg31) { in printCompactDWARFExpr()
229 uint64_t DwarfRegNum = Opcode - dwarf::DW_OP_reg0; in printCompactDWARFExpr()
235 } else if (Opcode >= dwarf::DW_OP_breg0 && in printCompactDWARFExpr()
236 Opcode <= dwarf::DW_OP_breg31) { in printCompactDWARFExpr()
237 int DwarfRegNum = Opcode - dwarf::DW_OP_breg0; in printCompactDWARFExpr()
249 OS << "<unknown op " << dwarf::OperationEncodingString(Opcode) << " (" in printCompactDWARFExpr()
250 << (int)Opcode << ")>"; in printCompactDWARFExpr()
278 DIDumpOptions DumpOpts, uint8_t Opcode, in prettyPrintRegisterOp() argument
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DMatchContext.h31 bool match(SDValue OpN, unsigned Opcode) const { in match() argument
32 return Opcode == OpN->getOpcode(); in match()
75 std::optional<unsigned> Opcode = ISD::getBaseOpcodeForVP( in getRootBaseOpcode() local
77 assert(Opcode.has_value()); in getRootBaseOpcode()
78 return *Opcode; in getRootBaseOpcode()
112 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand) { in getNode() argument
113 unsigned VPOpcode = *ISD::getVPForBaseOpcode(Opcode); in getNode()
120 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
122 unsigned VPOpcode = *ISD::getVPForBaseOpcode(Opcode); in getNode()
128 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1, in getNode() argument
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/freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/
H A DARMEHABIPrinter.h99 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx() local
100 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode, in Decode_00xxxxxx()
101 ((Opcode & 0x3f) << 2) + 4); in Decode_00xxxxxx()
105 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx() local
106 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode, in Decode_01xxxxxx()
107 ((Opcode & 0x3f) << 2) + 4); in Decode_01xxxxxx()
124 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101() local
125 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode); in Decode_10011101()
129 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111() local
130 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode); in Decode_10011111()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.h73 void EmitInt8(unsigned Opcode) { in EmitInt8() argument
74 Ops.push_back(Opcode & 0xff); in EmitInt8()
78 void EmitInt16(unsigned Opcode) { in EmitInt16() argument
79 Ops.push_back((Opcode >> 8) & 0xff); in EmitInt16()
80 Ops.push_back(Opcode & 0xff); in EmitInt16()
84 void emitBytes(const uint8_t *Opcode, size_t Size) { in emitBytes() argument
85 Ops.insert(Ops.end(), Opcode, Opcode + Size); in emitBytes()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp64 uint32_t Opcode; member
72 uint32_t Opcode; member
91 uint32_t Opcode; member
102 uint32_t Opcode; member
109 uint32_t Opcode; member
137 uint32_t Opcode; member
630 static bool buildOpFromWrapper(MachineIRBuilder &MIRBuilder, unsigned Opcode, in buildOpFromWrapper() argument
634 auto MIB = MIRBuilder.buildInstr(Opcode);
720 unsigned Opcode, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR) { in buildAtomicCompareExchangeInst() argument
722 return buildOpFromWrapper(MIRBuilder, Opcode, Call, in buildAtomicCompareExchangeInst()
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetTransformInfo.cpp54 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, in getArithmeticInstrCost() argument
60 Opcode, Ty, CostKind, Op1Info, Op2Info); in getArithmeticInstrCost()
63 switch (Opcode) { in getArithmeticInstrCost()
74 getArithmeticInstrCost(Opcode, VTy->getElementType(), CostKind) + in getArithmeticInstrCost()
83 unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, in getCastInstrCost() argument
85 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost()
90 return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); in getCastInstrCost()
94 return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); in getCastInstrCost()
141 return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I); in getCastInstrCost()
145 unsigned Opcode, Type *Ty, Align Alignment, unsigned AddressSpace, in getMemoryOpCost() argument
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