Lines Matching refs:Opcode
98 static unsigned log2LdstWidth(unsigned Opcode) { in log2LdstWidth() argument
99 switch (Opcode) { in log2LdstWidth()
123 static unsigned offsetMask(unsigned Opcode) { in offsetMask() argument
124 switch (Opcode) { in offsetMask()
148 static uint8_t compressedLDSTOffsetMask(unsigned Opcode) { in compressedLDSTOffsetMask() argument
149 return offsetMask(Opcode) << log2LdstWidth(Opcode); in compressedLDSTOffsetMask()
154 static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) { in compressibleSPOffset() argument
156 switch (log2LdstWidth(Opcode)) { in compressibleSPOffset()
168 static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) { in getBaseAdjustForCompression() argument
170 return Offset & ~compressedLDSTOffsetMask(Opcode); in getBaseAdjustForCompression()
234 const unsigned Opcode = MI.getOpcode(); in getRegImmPairPreventingCompression() local
242 int64_t NewBaseAdjust = getBaseAdjustForCompression(Offset, Opcode); in getRegImmPairPreventingCompression()
248 if (!compressibleSPOffset(Offset, Opcode) && NewBaseAdjust) in getRegImmPairPreventingCompression()
341 unsigned Opcode = MI.getOpcode(); in updateOperands() local
374 int64_t NewOffset = MOImm.getImm() & compressedLDSTOffsetMask(Opcode); in updateOperands()
419 unsigned Opcode = RISCV::FPR32RegClass.contains(RegImm.Reg) in runOnMachineFunction() local
422 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(Opcode), NewReg) in runOnMachineFunction()