178         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
184         int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
221   unsigned Opcode = MI.getOpcode();  in getMemoryOpOffset()  local
222   bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;  in getMemoryOpOffset()
226   if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||  in getMemoryOpOffset()
227       Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||  in getMemoryOpOffset()
228       Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||  in getMemoryOpOffset()
229       Opcode == ARM::LDRi12   || Opcode == ARM::STRi12)  in getMemoryOpOffset()
233   if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi ||  in getMemoryOpOffset()
234       Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)  in getMemoryOpOffset()
256 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) {  in getLoadStoreMultipleOpcode()  argument
257   switch (Opcode) {  in getLoadStoreMultipleOpcode()
341 static ARM_AM::AMSubMode getLoadStoreMultipleSubMode(unsigned Opcode) {  in getLoadStoreMultipleSubMode()  argument
342   switch (Opcode) {  in getLoadStoreMultipleSubMode()
630     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreMulti()  argument
650     if (Opcode == ARM::tLDRi)  in CreateLoadStoreMulti()
652     else if (Opcode == ARM::tSTRi)  in CreateLoadStoreMulti()
658   bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);  in CreateLoadStoreMulti()
668   } else if (Offset != 0 || Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) {  in CreateLoadStoreMulti()
671     if (!getLoadStoreMultipleOpcode(Opcode, Mode)) return nullptr;  in CreateLoadStoreMulti()
685     if (isi32Load(Opcode)) {  in CreateLoadStoreMulti()
695       if (!isLoadSingle(Opcode))  in CreateLoadStoreMulti()
730       (!isi32Store(Opcode) || !ContainsReg(Regs, Base));  in CreateLoadStoreMulti()
780   bool isDef = isLoadSingle(Opcode);  in CreateLoadStoreMulti()
784   Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);  in CreateLoadStoreMulti()
785   if (!Opcode)  in CreateLoadStoreMulti()
803     if (Opcode == ARM::tLDMIA) {  in CreateLoadStoreMulti()
806       Opcode = ARM::tLDMIA_UPD;  in CreateLoadStoreMulti()
809     MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));  in CreateLoadStoreMulti()
821     MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));  in CreateLoadStoreMulti()
837     int Offset, unsigned Base, bool BaseKill, unsigned Opcode,  in CreateLoadStoreDouble()  argument
841   bool IsLoad = isi32Load(Opcode);  in CreateLoadStoreDouble()
842   assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store");  in CreateLoadStoreDouble()
863   unsigned Opcode = First->getOpcode();  in MergeOpsUpdate()  local
864   bool IsLoad = isLoadSingle(Opcode);  in MergeOpsUpdate()
914                                    Opcode, Pred, PredReg, DL, Regs,  in MergeOpsUpdate()
918                                   Opcode, Pred, PredReg, DL, Regs, Cand.Instrs);  in MergeOpsUpdate()
943   if (isLoadSingle(Opcode)) {  in MergeOpsUpdate()
964     assert(isi32Store(Opcode) || Opcode == ARM::VSTRS || Opcode == ARM::VSTRD);  in MergeOpsUpdate()
992   unsigned Opcode = MI.getOpcode();  in mayCombineMisaligned()  local
993   if (!isi32Load(Opcode) && !isi32Store(Opcode))  in mayCombineMisaligned()
1007   unsigned Opcode = FirstMI->getOpcode();  in FormCandidates()  local
1008   bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);  in FormCandidates()
1028     if (STI->isCortexM3() && isi32Load(Opcode) &&  in FormCandidates()
1049     switch (Opcode) {  in FormCandidates()
1299   unsigned Opcode = MI->getOpcode();  in MergeBaseUpdateLSMultiple()  local
1314   ARM_AM::AMSubMode Mode = getLoadStoreMultipleSubMode(Opcode);  in MergeBaseUpdateLSMultiple()
1349   unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);  in MergeBaseUpdateLSMultiple()
1477   unsigned Opcode = MI->getOpcode();  in MergeBaseUpdateLoadStore()  local
1479   bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||  in MergeBaseUpdateLoadStore()
1480                 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);  in MergeBaseUpdateLoadStore()
1481   bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);  in MergeBaseUpdateLoadStore()
1482   if (isi32Load(Opcode) || isi32Store(Opcode))  in MergeBaseUpdateLoadStore()
1503     NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::add);  in MergeBaseUpdateLoadStore()
1505     NewOpc = getPreIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);  in MergeBaseUpdateLoadStore()
1511     NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::add);  in MergeBaseUpdateLoadStore()
1514       NewOpc = getPostIndexedLoadStoreOpcode(Opcode, ARM_AM::sub);  in MergeBaseUpdateLoadStore()
1524   bool isLd = isLoadSingle(Opcode);  in MergeBaseUpdateLoadStore()
1615   unsigned Opcode = MI.getOpcode();  in MergeBaseUpdateLSDouble()  local
1616   assert((Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) &&  in MergeBaseUpdateLSDouble()
1640     NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_PRE : ARM::t2STRD_PRE;  in MergeBaseUpdateLSDouble()
1645     NewOpc = Opcode == ARM::t2LDRDi8 ? ARM::t2LDRD_POST : ARM::t2STRD_POST;  in MergeBaseUpdateLSDouble()
1662   assert(TII->get(Opcode).getNumOperands() == 6 &&  in MergeBaseUpdateLSDouble()
1679   unsigned Opcode = MI.getOpcode();  in isMemoryOp()  local
1680   switch (Opcode) {  in isMemoryOp()
1764   unsigned Opcode = MI->getOpcode();  in FixInvalidRegPairOp()  local
1767   if (Opcode != ARM::LDRD && Opcode != ARM::STRD && Opcode != ARM::t2LDRDi8)  in FixInvalidRegPairOp()
1780     (Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8) && STI->isCortexM3();  in FixInvalidRegPairOp()
1782   bool NonConsecutiveRegs = (Opcode == ARM::LDRD || Opcode == ARM::STRD) &&  in FixInvalidRegPairOp()
1788   bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;  in FixInvalidRegPairOp()
1789   bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;  in FixInvalidRegPairOp()
1897       unsigned Opcode = MBBI->getOpcode();  in LoadStoreMultipleOpti()  local
1907         CurrOpc  = Opcode;  in LoadStoreMultipleOpti()
1913       if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {  in LoadStoreMultipleOpti()
1922         if (isLoadSingle(Opcode)) {  in LoadStoreMultipleOpti()
2001         unsigned Opcode = Merged->getOpcode();  in LoadStoreMultipleOpti()  local
2002         if (Opcode == ARM::t2STRDi8 || Opcode == ARM::t2LDRDi8)  in LoadStoreMultipleOpti()
2052     unsigned Opcode = PrevMI.getOpcode();  in MergeReturnIntoLDM()  local
2053     if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||  in MergeReturnIntoLDM()
2054         Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||  in MergeReturnIntoLDM()
2055         Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {  in MergeReturnIntoLDM()
2060       assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||  in MergeReturnIntoLDM()
2061               Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");  in MergeReturnIntoLDM()
2265   unsigned Opcode = Op0->getOpcode();  in CanFormLdStDWord()  local
2266   if (Opcode == ARM::LDRi12) {  in CanFormLdStDWord()
2268   } else if (Opcode == ARM::STRi12) {  in CanFormLdStDWord()
2270   } else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {  in CanFormLdStDWord()
2274   } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {  in CanFormLdStDWord()
2995 static bool isLegalOrConvertableAddressImm(unsigned Opcode, int Imm,  in isLegalOrConvertableAddressImm()  argument
2998   if (isLegalAddressImm(Opcode, Imm, TII))  in isLegalOrConvertableAddressImm()
3002   const MCInstrDesc &Desc = TII->get(Opcode);  in isLegalOrConvertableAddressImm()