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Searched refs:Op2 (Results 1 – 25 of 132) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp141 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
144 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
145 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
152 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
153 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
188 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue() local
192 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
198 if (Op2.isImm()) { in getRiMemoryOpValue()
199 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
202 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp217 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
230 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction()
235 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
245 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction()
323 unsigned Op1, Op2; in Decode2RInstruction() local
324 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
329 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
336 unsigned Op1, Op2; in Decode2RImmInstruction() local
337 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
342 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
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/freebsd/sys/contrib/dev/acpica/compiler/
H A Dasltree.c651 ACPI_PARSE_OBJECT *Op2) in TrLinkPeerOp() argument
659 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode) : NULL); in TrLinkPeerOp()
662 if ((!Op1) && (!Op2)) in TrLinkPeerOp()
670 if (!Op2) in TrLinkPeerOp()
677 return (Op2); in TrLinkPeerOp()
680 if (Op1 == Op2) in TrLinkPeerOp()
690 Op1->Asl.Parent = Op2->Asl.Parent; in TrLinkPeerOp()
703 Next->Asl.Next = Op2; in TrLinkPeerOp()
788 ACPI_PARSE_OBJECT *Op2) in TrLinkChildOp() argument
796 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode): NULL); in TrLinkChildOp()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp253 const MachineMemOperand &Op2, in alias() argument
255 if (!Op1.getValue() || !Op2.getValue() || !Op1.getSize().hasValue() || in alias()
256 !Op2.getSize().hasValue()) in alias()
259 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
261 int64_t Overlapb = Op2.getSize().getValue() + Op2.getOffset() - MinOffset; in alias()
266 MemoryLocation(Op2.getValue(), Overlapb, in alias()
267 UseTBAA ? Op2.getAAInfo() : AAMDNodes())); in alias()
279 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local
280 if (alias(*Op1, *Op2, UseTBAA)) in alias()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp163 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) { in isSameOperand() argument
164 if (Op1.getType() != Op2.getType()) in isSameOperand()
169 return Op1.getReg() == Op2.getReg(); in isSameOperand()
171 return Op1.getImm() == Op2.getImm(); in isSameOperand()
287 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr() local
294 if (Op2.isImm()) { in isSuitableAluInstr()
307 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
308 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
309 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr()
311 } else if (Op2.isReg()) { in isSuitableAluInstr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp157 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
163 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
164 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
175 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
178 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DPPC.cpp418 Value *Op2 = EmitScalarExpr(E->getArg(2)); in EmitPPCBuiltinExpr() local
425 Value *StVec = Op2; in EmitPPCBuiltinExpr()
430 StVec = Builder.CreateShuffleVector(Op2, Op2, RevMask); in EmitPPCBuiltinExpr()
433 StVec, Address(Op0, Op2->getType(), CharUnits::fromQuantity(1))); in EmitPPCBuiltinExpr()
458 Op2, llvm::FixedVectorType::get(ConvTy, NumElts)); in EmitPPCBuiltinExpr()
538 Value *Op2 = EmitScalarExpr(E->getArg(2)); in EmitPPCBuiltinExpr() local
547 ConstantInt *ArgCI = dyn_cast<ConstantInt>(Op2); in EmitPPCBuiltinExpr()
581 Op2 = ConstantInt::getSigned(Int32Ty, ConstArg); in EmitPPCBuiltinExpr()
589 Builder.CreateCall(CGM.getIntrinsic(ID), {Op0, Op1, Op2}), ResultType); in EmitPPCBuiltinExpr()
624 Value *Op2 = EmitScalarExpr(E->getArg(2)); in EmitPPCBuiltinExpr() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp119 MachineOperand &Op2 = A->getOperand(2); in optimizeVccBranch() local
120 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { in optimizeVccBranch()
126 if (Op2.isImm() && !(Op2.getImm() == -1 || Op2.getImm() == 0)) in optimizeVccBranch()
131 if (Op2.isReg()) { in optimizeVccBranch()
132 SReg = Op2.getReg(); in optimizeVccBranch()
161 if (!ReadsSreg && Op2.isKill()) { in optimizeVccBranch()
165 } else if (Op2.isImm()) { in optimizeVccBranch()
166 MaskValue = Op2.getImm(); in optimizeVccBranch()
H A DSIOptimizeExecMaskingPreRA.cpp163 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair() local
164 if (Op1->isImm() && Op2->isReg()) in optimizeVcndVcmpPair()
165 std::swap(Op1, Op2); in optimizeVcndVcmpPair()
166 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) in optimizeVcndVcmpPair()
182 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
184 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || in optimizeVcndVcmpPair()
185 Op1->getImm() != 0 || Op2->getImm() != 1) in optimizeVcndVcmpPair()
/freebsd/contrib/llvm-project/llvm/lib/MC/MCParser/
H A DMCTargetAsmParser.cpp54 const MCParsedAsmOperand &Op2) const { in areEqualRegs()
55 return Op1.isReg() && Op2.isReg() && Op1.getReg() == Op2.getReg(); in areEqualRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h29 SDValue Chain, SDValue Op1, SDValue Op2,
36 SDValue Op1, SDValue Op2, SDValue Op3,
41 SDValue Chain, SDValue Op1, SDValue Op2,
H A DWebAssemblyPeephole.cpp141 const auto &Op2 = MI.getOperand(2); in runOnMachineFunction() local
142 if (!Op2.isReg()) in runOnMachineFunction()
147 Register NewReg = Op2.getReg(); in runOnMachineFunction()
H A DWebAssemblySelectionDAGInfo.cpp53 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument
56 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, in EmitTargetCodeForMemmove()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h77 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
93 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove() argument
107 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
120 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
157 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp295 BPFOperand &Op2 = (BPFOperand &)*Operands[2]; in PreMatchCheck() local
297 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
299 && (Op2.getToken() == "-" || Op2.getToken() == "be16" in PreMatchCheck()
300 || Op2.getToken() == "be32" || Op2.getToken() == "be64" in PreMatchCheck()
301 || Op2.getToken() == "le16" || Op2.getToken() == "le32" in PreMatchCheck()
302 || Op2.getToken() == "le64") in PreMatchCheck()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp338 const MachineOperand &Op2 = MI->getOperand(2); in profit() local
340 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0; in profit()
720 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
737 if (!Op2.isReg()) { in splitCombine()
739 .add(Op2); in splitCombine()
742 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
772 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
773 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift()
774 int64_t Sh64 = Op2.getImm(); in splitShift()
896 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanPatternMatch.h339 m_VPInstruction(const Op0_t &Op0, const Op1_t &Op1, const Op2_t &Op2) { in m_VPInstruction() argument
341 {Op0, Op1, Op2}); in m_VPInstruction()
358 m_VPInstruction(const Op0_t &Op0, const Op1_t &Op1, const Op2_t &Op2, in m_VPInstruction() argument
361 {Op0, Op1, Op2, Op3}); in m_VPInstruction()
483 m_Select(const Op0_t &Op0, const Op1_t &Op1, const Op2_t &Op2) { in m_Select() argument
485 {Op0, Op1, Op2}); in m_Select()
521 m_ScalarIVSteps(const Op0_t &Op0, const Op1_t &Op1, const Op2_t &Op2) { in m_ScalarIVSteps() argument
522 return VPScalarIVSteps_match<Op0_t, Op1_t, Op2_t>({Op0, Op1, Op2}); in m_ScalarIVSteps()
531 m_DerivedIV(const Op0_t &Op0, const Op1_t &Op1, const Op2_t &Op2) { in m_DerivedIV() argument
532 return VPDerivedIV_match<Op0_t, Op1_t, Op2_t>({Op0, Op1, Op2}); in m_DerivedIV()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SystemOperands.td688 // Name, Op1, Op2
712 // Name, Op1, Op2, Crm_high
1023 // Op0 Op1 CRn CRm Op2
1096 // Op0 Op1 CRn CRm Op2
1135 // Op0 Op1 CRn CRm Op2
1146 // Op0 Op1 CRn CRm Op2
1152 // Op0 Op1 CRn CRm Op2
1157 // Op0 Op1 CRn CRm Op2
1164 // Op0 Op1 CRn CRm Op2
1201 // Op0 Op1 CRn CRm Op2
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp309 auto Op2 = N->getOperand(2); in selectAddCarry() local
313 if (isNullConstant(Op2)) { in selectAddCarry()
319 } else if (isOneConstant(Op2)) { in selectAddCarry()
328 Dl, {Type0, Type1}, {Op0, Op1, Op2}); in selectAddCarry()
352 auto Op2 = N->getOperand(2); in selectSubCarry() local
356 if (isNullConstant(Op2)) { in selectSubCarry()
362 } else if (isOneConstant(Op2)) { in selectSubCarry()
369 auto CarryIn = InvertCarryFlag(Subtarget, CurDAG, Dl, Op2); in selectSubCarry()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp153 const MCOperand &Op2 = MI->getOperand(opNum + 1); in printMemOperand() local
164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) || in printMemOperand()
165 (Op2.isImm() && Op2.getImm() == 0)); in printMemOperand()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DBypassSlowDivision.cpp86 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
327 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { in insertOperandRuntimeCheck() argument
328 assert((Op1 || Op2) && "Nothing to check"); in insertOperandRuntimeCheck()
333 if (Op1 && Op2) in insertOperandRuntimeCheck()
334 OrV = Builder.CreateOr(Op1, Op2); in insertOperandRuntimeCheck()
336 OrV = Op1 ? Op1 : Op2; in insertOperandRuntimeCheck()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp339 const MachineOperand &Op2 = OpList2[i]; in identicalOperands() local
342 << "Op2: " << Op2 << "\n"); in identicalOperands()
344 if (Op1.isIdenticalTo(Op2)) { in identicalOperands()
360 if (Op1.isReg() && Op2.isReg() && Op1.getReg().isVirtual() && in identicalOperands()
361 Op2.getReg().isVirtual()) { in identicalOperands()
363 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg()); in identicalOperands()
H A DPPCMacroFusion.cpp73 const MachineOperand &Op2 = SecondMI.getOperand(SecondMIOpIndex); in matchingRegOps() local
74 if (!Op1.isReg() || !Op2.isReg()) in matchingRegOps()
77 return Op1.getReg() == Op2.getReg(); in matchingRegOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp180 MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1); in getMemoryOpValue() local
181 assert(Op2.isImm() && "Second operand is not immediate."); in getMemoryOpValue()
182 Encoding |= Op2.getImm() & 0xffff; in getMemoryOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp113 bool alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2) const;
518 const MachineMemOperand &Op2) const { in alias()
519 if (!Op1.getValue() || !Op2.getValue()) in alias()
522 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
524 int64_t Overlapb = Op2.getSize().getValue() + Op2.getOffset() - MinOffset; in alias()
528 MemoryLocation(Op2.getValue(), Overlapb, Op2.getAAInfo())); in alias()

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