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Searched refs:Op2 (Results 1 – 25 of 133) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp143 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits() local
146 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
147 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
154 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
155 (Op2.isReg() && Op2 in adjustPqBits()
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1); getRiMemoryOpValue() local
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1); getRrMemoryOpValue() local
261 const MCOperand Op2 = Inst.getOperand(OpNo + 1); getSplsOpValue() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp216 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { in Decode2OpInstruction() argument
229 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); in Decode2OpInstruction()
234 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, in Decode3OpInstruction() argument
244 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2); in Decode3OpInstruction()
322 unsigned Op1, Op2; in Decode2RInstruction() local
323 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RInstruction()
328 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RInstruction()
335 unsigned Op1, Op2; in Decode2RImmInstruction() local
336 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); in Decode2RImmInstruction()
341 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); in Decode2RImmInstruction()
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/freebsd/sys/contrib/dev/acpica/compiler/
H A Dasltree.c651 ACPI_PARSE_OBJECT *Op2) in TrLinkPeerOp() argument
659 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode) : NULL); in TrLinkPeerOp()
662 if ((!Op1) && (!Op2)) in TrLinkPeerOp()
670 if (!Op2) in TrLinkPeerOp()
677 return (Op2); in TrLinkPeerOp()
680 if (Op1 == Op2) in TrLinkPeerOp()
690 Op1->Asl.Parent = Op2->Asl.Parent; in TrLinkPeerOp()
703 Next->Asl.Next = Op2; in TrLinkPeerOp()
788 ACPI_PARSE_OBJECT *Op2) in TrLinkChildOp() argument
796 Op2, Op2 ? UtGetOpName(Op2->Asl.ParseOpcode): NULL); in TrLinkChildOp()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DDFAPacketizer.cpp253 const MachineMemOperand &Op2, in alias() argument
255 if (!Op1.getValue() || !Op2.getValue() || !Op1.getSize().hasValue() || in alias()
256 !Op2.getSize().hasValue()) in alias()
259 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
261 int64_t Overlapb = Op2.getSize().getValue() + Op2.getOffset() - MinOffset; in alias()
266 MemoryLocation(Op2.getValue(), Overlapb, in alias()
267 UseTBAA ? Op2.getAAInfo() : AAMDNodes())); in alias()
279 for (const MachineMemOperand *Op2 : MI2.memoperands()) in alias() local
280 if (alias(*Op1, *Op2, UseTBAA)) in alias()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp169 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) {
170 if (Op1.getType() != Op2.getType()) in isSameOperand() argument
175 return Op1.getReg() == Op2.getReg(); in isSameOperand()
177 return Op1.getImm() == Op2.getImm(); in isSameOperand()
293 MachineOperand &Op2 = AluIter->getOperand(2); in isSuitableAluInstr()
300 if (Op2.isImm()) { in isSuitableAluInstr()
311 // Check that the Op2 would fit in the immediate field of the in isSuitableAluInstr()
313 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
314 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
315 Offset.getImm() == Op2 in isSuitableAluInstr()
294 MachineOperand &Op2 = AluIter->getOperand(2); isSuitableAluInstr() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp158 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
164 Ops[5].getAsInteger(10, Op2); in parseGenericRegister()
165 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
176 uint32_t Op2 = Bits & 0x7; in genericRegisterString() local
179 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp117 MachineOperand &Op2 = A->getOperand(2); in optimizeVccBranch() local
118 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) { in optimizeVccBranch()
124 if (Op2.isImm() && !(Op2.getImm() == -1 || Op2.getImm() == 0)) in optimizeVccBranch()
129 if (Op2.isReg()) { in optimizeVccBranch()
130 SReg = Op2.getReg(); in optimizeVccBranch()
159 if (!ReadsSreg && Op2.isKill()) { in optimizeVccBranch()
163 } else if (Op2.isImm()) { in optimizeVccBranch()
164 MaskValue = Op2.getImm(); in optimizeVccBranch()
H A DSIOptimizeExecMaskingPreRA.cpp155 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair() local
156 if (Op1->isImm() && Op2->isReg()) in optimizeVcndVcmpPair()
157 std::swap(Op1, Op2); in optimizeVcndVcmpPair()
158 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1) in optimizeVcndVcmpPair()
174 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
176 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() || in optimizeVcndVcmpPair()
177 Op1->getImm() != 0 || Op2->getImm() != 1) in optimizeVcndVcmpPair()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGTargetInfo.h53 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcpy() argument
69 SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, in EmitTargetCodeForMemmove() argument
83 SDValue Op2, SDValue Op3, in EmitTargetCodeForMemset() argument
96 SDValue Op1, SDValue Op2, SDValue Op3, in EmitTargetCodeForMemcmp() argument
133 SDValue Op1, SDValue Op2, in EmitTargetCodeForStrcmp() argument
/freebsd/contrib/llvm-project/llvm/lib/MC/MCParser/
H A DMCTargetAsmParser.cpp54 const MCParsedAsmOperand &Op2) const { in areEqualRegs()
55 return Op1.isReg() && Op2.isReg() && Op1.getReg() == Op2.getReg(); in areEqualRegs()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h26 SDValue Chain, SDValue Op1, SDValue Op2,
33 SDValue Op1, SDValue Op2, SDValue Op3,
38 SDValue Chain, SDValue Op1, SDValue Op2,
H A DWebAssemblyPeephole.cpp141 const auto &Op2 = MI.getOperand(2); in runOnMachineFunction() local
142 if (!Op2.isReg()) in runOnMachineFunction()
147 Register NewReg = Op2.getReg(); in runOnMachineFunction()
H A DWebAssemblySelectionDAGInfo.cpp37 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove() argument
40 return EmitTargetCodeForMemcpy(DAG, DL, Chain, Op1, Op2, Op3, in EmitTargetCodeForMemmove()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp292 BPFOperand &Op2 = (BPFOperand &)*Operands[2]; in PreMatchCheck() local
294 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg() in PreMatchCheck()
296 && (Op2.getToken() == "-" || Op2.getToken() == "be16" in PreMatchCheck()
297 || Op2.getToken() == "be32" || Op2.getToken() == "be64" in PreMatchCheck()
298 || Op2.getToken() == "le16" || Op2.getToken() == "le32" in PreMatchCheck()
299 || Op2.getToken() == "le64") in PreMatchCheck()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SystemOperands.td428 // Name, Op1, Op2
452 // Name, Op1, Op2, Crm_high
701 // Op0 Op1 CRn CRm Op2
774 // Op0 Op1 CRn CRm Op2
813 // Op0 Op1 CRn CRm Op2
824 // Op0 Op1 CRn CRm Op2
830 // Op0 Op1 CRn CRm Op2
835 // Op0 Op1 CRn CRm Op2
842 // Op0 Op1 CRn CRm Op2
879 // Op0 Op1 CRn CRm Op2
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp344 const MachineOperand &Op2 = MI->getOperand(2); in profit() local
346 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0; in profit()
726 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
743 if (!Op2.isReg()) { in splitCombine()
745 .add(Op2); in splitCombine()
748 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
778 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
779 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift()
780 int64_t Sh64 = Op2.getImm(); in splitShift()
902 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp153 const MCOperand &Op2 = MI->getOperand(opNum + 1); in printMemOperand() local
164 PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) || in printMemOperand()
165 (Op2.isImm() && Op2.getImm() == 0)); in printMemOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp309 auto Op2 = N->getOperand(2); in selectAddCarry() local
313 if (isNullConstant(Op2)) { in selectAddCarry()
319 } else if (isOneConstant(Op2)) { in selectAddCarry()
328 Dl, {Type0, Type1}, {Op0, Op1, Op2}); in selectAddCarry()
352 auto Op2 = N->getOperand(2); in selectSubCarry() local
356 if (isNullConstant(Op2)) { in selectSubCarry()
362 } else if (isOneConstant(Op2)) { in selectSubCarry()
369 auto CarryIn = InvertCarryFlag(Subtarget, CurDAG, Dl, Op2); in selectSubCarry()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp341 const MachineOperand &Op2 = OpList2[i]; in identicalOperands() local
344 << "Op2: " << Op2 << "\n"); in identicalOperands()
346 if (Op1.isIdenticalTo(Op2)) { in identicalOperands()
362 if (Op1.isReg() && Op2.isReg() && Op1.getReg().isVirtual() && in identicalOperands()
363 Op2.getReg().isVirtual()) { in identicalOperands()
365 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg()); in identicalOperands()
H A DPPCMacroFusion.cpp73 const MachineOperand &Op2 = SecondMI.getOperand(SecondMIOpIndex); in matchingRegOps() local
74 if (!Op1.isReg() || !Op2.isReg()) in matchingRegOps()
77 return Op1.getReg() == Op2.getReg(); in matchingRegOps()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DBypassSlowDivision.cpp87 Value *insertOperandRuntimeCheck(Value *Op1, Value *Op2);
328 Value *FastDivInsertionTask::insertOperandRuntimeCheck(Value *Op1, Value *Op2) { in insertOperandRuntimeCheck() argument
329 assert((Op1 || Op2) && "Nothing to check"); in insertOperandRuntimeCheck()
334 if (Op1 && Op2) in insertOperandRuntimeCheck()
335 OrV = Builder.CreateOr(Op1, Op2); in insertOperandRuntimeCheck()
337 OrV = Op1 ? Op1 : Op2; in insertOperandRuntimeCheck()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp166 MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1); in getMemoryOpValue()
167 assert(Op2.isImm() && "Second operand is not immediate."); in getMemoryOpValue()
168 Encoding |= Op2.getImm() & 0xffff;
163 MCOperand Op2 = MI.getOperand(MemOpStartIndex + 1); getMemoryOpValue() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp114 bool alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2) const;
519 const MachineMemOperand &Op2) const { in alias()
520 if (!Op1.getValue() || !Op2.getValue()) in alias()
523 int64_t MinOffset = std::min(Op1.getOffset(), Op2.getOffset()); in alias()
525 int64_t Overlapb = Op2.getSize().getValue() + Op2.getOffset() - MinOffset; in alias()
529 MemoryLocation(Op2.getValue(), Overlapb, Op2.getAAInfo())); in alias()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h1679 T1 Op2; member
1681 TwoOps_match(const T0 &Op1, const T1 &Op2) : Op1(Op1), Op2(Op2) {} in TwoOps_match()
1686 return Op1.match(I->getOperand(0)) && Op2.match(I->getOperand(1)); in match()
1696 T1 Op2; member
1699 ThreeOps_match(const T0 &Op1, const T1 &Op2, const T2 &Op3) in ThreeOps_match()
1700 : Op1(Op1), Op2(Op2), Op3(Op3) {} in ThreeOps_match()
1705 return Op1.match(I->getOperand(0)) && Op2.match(I->getOperand(1)) && in match()
1782 T1 Op2; member
1785 Shuffle_match(const T0 &Op1, const T1 &Op2, const T2 &Mask) in Shuffle_match()
1786 : Op1(Op1), Op2(Op2), Mask(Mask) {} in Shuffle_match()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp296 ICToken Op2 = OperandStack.pop_back_val(); in execute() local
303 Val = Op1.second + Op2.second; in execute()
307 Val = Op1.second - Op2.second; in execute()
311 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
313 Val = Op1.second * Op2.second; in execute()
317 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
319 assert (Op2.second != 0 && "Division by zero!"); in execute()
320 Val = Op1.second / Op2.second; in execute()
324 assert (Op1.first == IC_IMM && Op2.first == IC_IMM && in execute()
326 Val = Op1.second % Op2.second; in execute()
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