Lines Matching refs:Op2
344 const MachineOperand &Op2 = MI->getOperand(2); in profit() local
346 int32_t Prof2 = Op2.isImm() ? profitImm(Op2.getImm()) : 0; in profit()
726 MachineOperand &Op2 = MI->getOperand(2); in splitCombine() local
743 if (!Op2.isReg()) { in splitCombine()
745 .add(Op2); in splitCombine()
748 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
778 MachineOperand &Op2 = MI->getOperand(2); in splitShift() local
779 assert(Op0.isReg() && Op1.isReg() && Op2.isImm()); in splitShift()
780 int64_t Sh64 = Op2.getImm(); in splitShift()
902 MachineOperand &Op2 = MI->getOperand(2); in splitAslOr() local
904 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); in splitAslOr()
918 unsigned RS2 = getRegState(Op2); in splitAslOr()
942 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR); in splitAslOr()
945 .addReg(Op2.getReg(), RS2, HiSR); in splitAslOr()
949 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
953 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR) in splitAslOr()
962 .addReg(Op2.getReg(), RS2, HiSR) in splitAslOr()
973 .addReg(Op2.getReg(), RS2, LoSR); in splitAslOr()
984 .addReg(Op2.getReg(), RS2, LoSR) in splitAslOr()