Lines Matching refs:Op2
143 const MCOperand Op2 = Inst.getOperand(2);
146 ((Op2.isImm() && Op2.getImm() != 0) ||
147 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
154 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
155 (Op2.isReg() && Op2.getReg() != Lanai::R0)))
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
194 assert((Op2.isImm() || Op2.isExpr()) &&
200 if (Op2.isImm()) {
201 assert(isInt<16>(Op2.getImm()) &&
204 Encoding |= (Op2.getImm() & 0xffff);
205 if (Op2.getImm() != 0) {
212 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
227 assert(Op2.isReg() && "Second operand is not register.");
228 Encoding |= (getLanaiRegisterNumbering(Op2.getReg()) << 10);
261 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
265 assert((Op2.isImm() || Op2.isExpr()) &&
271 if (Op2.isImm()) {
272 assert(isInt<10>(Op2.getImm()) &&
275 Encoding |= (Op2.getImm() & 0x3ff);
276 if (Op2.getImm() != 0) {
283 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);