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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXReplaceImageHandles.cpp15 #include "NVPTX.h"
40 return "NVPTX Replace Image Handles"; in getPassName()
78 case NVPTX::SULD_1D_I8_CLAMP_R: in suldRegisterToIndexOpcode()
79 return NVPTX::SULD_1D_I8_CLAMP_I; in suldRegisterToIndexOpcode()
80 case NVPTX::SULD_1D_I16_CLAMP_R: in suldRegisterToIndexOpcode()
81 return NVPTX::SULD_1D_I16_CLAMP_I; in suldRegisterToIndexOpcode()
82 case NVPTX::SULD_1D_I32_CLAMP_R: in suldRegisterToIndexOpcode()
83 return NVPTX::SULD_1D_I32_CLAMP_I; in suldRegisterToIndexOpcode()
84 case NVPTX::SULD_1D_I64_CLAMP_R: in suldRegisterToIndexOpcode()
85 return NVPTX in suldRegisterToIndexOpcode()
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H A DNVPTXISelDAGToDAG.cpp565 (N->getValueType(0) == MVT::f16 ? NVPTX::LOAD_CONST_F16 in tryConstantFP()
566 : NVPTX::LOAD_CONST_BF16), in tryConstantFP()
575 using NVPTX::PTXCmpMode::CmpMode; in getPTXCmpMode()
624 PTXCmpMode |= NVPTX::PTXCmpMode::FTZ_FLAG; in getPTXCmpMode()
634 NVPTX::SETP_f16x2rr, DL, MVT::i1, MVT::i1, N->getOperand(0), in SelectSETP_F16X2()
645 NVPTX::SETP_bf16x2rr, DL, MVT::i1, MVT::i1, N->getOperand(0), in SelectSETP_BF16X2()
688 CurDAG->getMachineNode(NVPTX::I32toV2I16, SDLoc(N), EltVT, EltVT, Vector); in tryEXTRACT_VECTOR_ELEMENT()
701 return NVPTX::PTXLdStInstCode::GENERIC; in getCodeAddrSpace()
705 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL; in getCodeAddrSpace()
706 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL; in getCodeAddrSpace()
[all …]
H A DNVPTXInstrInfo.cpp44 if (DestRC == &NVPTX::Int1RegsRegClass) { in copyPhysReg()
45 Op = NVPTX::IMOV1rr; in copyPhysReg()
46 } else if (DestRC == &NVPTX::Int16RegsRegClass) { in copyPhysReg()
47 Op = NVPTX::IMOV16rr; in copyPhysReg()
48 } else if (DestRC == &NVPTX::Int32RegsRegClass) { in copyPhysReg()
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr in copyPhysReg()
50 : NVPTX::BITCONVERT_32_F2I); in copyPhysReg()
51 } else if (DestRC == &NVPTX::Int64RegsRegClass) { in copyPhysReg()
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr in copyPhysReg()
53 : NVPTX::BITCONVERT_64_F2I); in copyPhysReg()
[all …]
H A DNVPTXRegisterInfo.cpp30 if (RC == &NVPTX::Float32RegsRegClass) in getNVPTXRegClassName()
32 if (RC == &NVPTX::Float64RegsRegClass) in getNVPTXRegClassName()
34 if (RC == &NVPTX::Int128RegsRegClass) in getNVPTXRegClassName()
36 if (RC == &NVPTX::Int64RegsRegClass) in getNVPTXRegClassName()
56 if (RC == &NVPTX::Int32RegsRegClass) in getNVPTXRegClassName()
58 if (RC == &NVPTX::Int16RegsRegClass) in getNVPTXRegClassName()
60 if (RC == &NVPTX::Int1RegsRegClass) in getNVPTXRegClassName()
62 if (RC == &NVPTX::SpecialRegsRegClass) in getNVPTXRegClassName()
68 if (RC == &NVPTX::Float32RegsRegClass) in getNVPTXRegClassStr()
70 if (RC == &NVPTX::Float64RegsRegClass) in getNVPTXRegClassStr()
[all …]
H A DNVPTXProxyRegErasure.cpp72 case NVPTX::ProxyRegI1: in runOnMachineFunction()
73 case NVPTX::ProxyRegI16: in runOnMachineFunction()
74 case NVPTX::ProxyRegI32: in runOnMachineFunction()
75 case NVPTX::ProxyRegI64: in runOnMachineFunction()
76 case NVPTX::ProxyRegF32: in runOnMachineFunction()
77 case NVPTX::ProxyRegF64: in runOnMachineFunction()
H A DNVPTXFrameLowering.cpp53 (Is64Bit ? NVPTX::cvta_local_64 : NVPTX::cvta_local); in emitPrologue()
55 (Is64Bit ? NVPTX::MOV_DEPOT_ADDR_64 : NVPTX::MOV_DEPOT_ADDR); in emitPrologue()
76 FrameReg = NVPTX::VRDepot; in getFrameIndexReference()
H A DNVPTX.td1 //===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen -*-==//
8 // This is the top level entry point for the NVPTX target.
49 // NVPTX supported processors.
80 def NVPTX : Target {
H A DNVPTXInstrFormats.td1 //===- NVPTXInstrFormats.td - NVPTX Instruction Formats-------*- tblgen -*-===//
10 // Describe NVPTX instructions format
20 // Generic NVPTX Format
26 let Namespace = "NVPTX";
H A DNVPTXPeephole.cpp79 if (Root.getOpcode() != NVPTX::cvta_to_local_64 && in isCVTAToLocalCombinationCandidate()
80 Root.getOpcode() != NVPTX::cvta_to_local) in isCVTAToLocalCombinationCandidate()
92 (GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi64 && in isCVTAToLocalCombinationCandidate()
93 GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi)) { in isCVTAToLocalCombinationCandidate()
H A DNVPTXRegisterInfo.td1 //===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
14 let Namespace = "NVPTX";
18 : RegisterClass <"NVPTX", regTypes, alignment, regList>;
66 // 128-bit regs are not defined as general regs in NVPTX. They are used for inlineASM only.
H A DNVPTXPassRegistry.def1 //===- NVPTXPassRegistry.def - Registry of NVPTX passes ---------*- C++ -*-===//
10 // NVPTX backend.
H A DNVPTXTargetMachine.h28 NVPTX::DrvInterface drvInterface;
47 NVPTX::DrvInterface getDrvInterface() const { return drvInterface; } in getDrvInterface()
H A DNVPTXAsmPrinter.cpp223 if (MI->getOpcode() == NVPTX::CALL_PROTOTYPE) { in lowerToMCInst()
306 if (RC == &NVPTX::Int1RegsRegClass) { in encodeVirtualRegister()
308 } else if (RC == &NVPTX::Int16RegsRegClass) { in encodeVirtualRegister()
310 } else if (RC == &NVPTX::Int32RegsRegClass) { in encodeVirtualRegister()
312 } else if (RC == &NVPTX::Int64RegsRegClass) { in encodeVirtualRegister()
314 } else if (RC == &NVPTX::Float32RegsRegClass) { in encodeVirtualRegister()
316 } else if (RC == &NVPTX::Float64RegsRegClass) { in encodeVirtualRegister()
318 } else if (RC == &NVPTX::Int128RegsRegClass) { in encodeVirtualRegister()
898 if (NTM.getDrvInterface() == NVPTX::NVCL) in emitHeader()
975 if (static_cast<NVPTXTargetMachine &>(TM).getDrvInterface() == NVPTX::CUDA) { in emitLinkageDirective()
[all …]
H A DNVPTXSubtarget.cpp1 //===- NVPTXSubtarget.cpp - NVPTX Subtarget Information -------------------===//
9 // This file implements the NVPTX specific subclass of TargetSubtarget.
27 cl::desc("NVPTX Specific: Disable generation of f16 math ops."),
62 if (TM.getDrvInterface() == NVPTX::CUDA) in hasImageHandles()
H A DNVPTXLowerArgs.cpp568 if (TM.getDrvInterface() == NVPTX::CUDA) { in runOnKernelFunction()
595 else if (TM.getDrvInterface() == NVPTX::CUDA) in runOnKernelFunction()
598 TM.getDrvInterface() == NVPTX::CUDA) { in runOnKernelFunction()
H A DNVPTXTargetMachine.cpp140 drvInterface = NVPTX::NVCL; in NVPTXTargetMachine()
142 drvInterface = NVPTX::CUDA; in NVPTXTargetMachine()
H A DNVPTX.h72 namespace NVPTX {
H A DNVPTXISelLowering.cpp479 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass); in NVPTXTargetLowering()
480 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
481 addRegisterClass(MVT::v2i16, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
482 addRegisterClass(MVT::v4i8, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
483 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
484 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass); in NVPTXTargetLowering()
485 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass); in NVPTXTargetLowering()
486 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass); in NVPTXTargetLowering()
487 addRegisterClass(MVT::f16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
488 addRegisterClass(MVT::v2f16, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
[all …]
H A DNVPTXAsmPrinter.h253 NVPTX::CUDA) {} in NVPTXAsmPrinter()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXInstPrinter.cpp102 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) in printCvtMode()
106 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) in printCvtMode()
110 if (Imm & NVPTX::PTXCvtMode::RELU_FLAG) in printCvtMode()
114 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { in printCvtMode()
117 case NVPTX::PTXCvtMode::NONE: in printCvtMode()
119 case NVPTX::PTXCvtMode::RNI: in printCvtMode()
122 case NVPTX::PTXCvtMode::RZI: in printCvtMode()
125 case NVPTX::PTXCvtMode::RMI: in printCvtMode()
128 case NVPTX::PTXCvtMode::RPI: in printCvtMode()
131 case NVPTX::PTXCvtMode::RN: in printCvtMode()
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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaNVPTX.cpp25 case NVPTX::BI__nvvm_cp_async_ca_shared_global_4: in CheckNVPTXBuiltinFunctionCall()
26 case NVPTX::BI__nvvm_cp_async_ca_shared_global_8: in CheckNVPTXBuiltinFunctionCall()
27 case NVPTX::BI__nvvm_cp_async_ca_shared_global_16: in CheckNVPTXBuiltinFunctionCall()
28 case NVPTX::BI__nvvm_cp_async_cg_shared_global_16: in CheckNVPTXBuiltinFunctionCall()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp19752 case NVPTX::BI__hmma_m16n16k16_ld_a: in getNVPTXMmaLdstInfo()
19754 case NVPTX::BI__hmma_m16n16k16_ld_b: in getNVPTXMmaLdstInfo()
19756 case NVPTX::BI__hmma_m16n16k16_ld_c_f16: in getNVPTXMmaLdstInfo()
19758 case NVPTX::BI__hmma_m16n16k16_ld_c_f32: in getNVPTXMmaLdstInfo()
19760 case NVPTX::BI__hmma_m32n8k16_ld_a: in getNVPTXMmaLdstInfo()
19762 case NVPTX::BI__hmma_m32n8k16_ld_b: in getNVPTXMmaLdstInfo()
19764 case NVPTX::BI__hmma_m32n8k16_ld_c_f16: in getNVPTXMmaLdstInfo()
19766 case NVPTX::BI__hmma_m32n8k16_ld_c_f32: in getNVPTXMmaLdstInfo()
19768 case NVPTX::BI__hmma_m8n32k16_ld_a: in getNVPTXMmaLdstInfo()
19770 case NVPTX::BI__hmma_m8n32k16_ld_b: in getNVPTXMmaLdstInfo()
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/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DCuda.cpp378 void NVPTX::Assembler::ConstructJob(Compilation &C, const JobAction &JA, in ConstructJob()
524 void NVPTX::FatBinary::ConstructJob(Compilation &C, const JobAction &JA, in ConstructJob()
575 void NVPTX::Linker::ConstructJob(Compilation &C, const JobAction &JA, in ConstructJob()
642 void NVPTX::getNVPTXTargetFeatures(const Driver &D, const llvm::Triple &Triple, in getNVPTXTargetFeatures()
977 return new tools::NVPTX::Assembler(*this); in buildAssembler()
981 return new tools::NVPTX::Linker(*this); in buildLinker()
985 return new tools::NVPTX::Assembler(*this); in buildAssembler()
989 return new tools::NVPTX::FatBinary(*this); in buildLinker()
H A DCuda.h81 namespace NVPTX {
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DTargetBuiltins.h103 namespace NVPTX {
371 PPC::LastTSBuiltin, NVPTX::LastTSBuiltin, AMDGPU::LastTSBuiltin,

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