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Searched refs:NVPTX (Results 1 – 25 of 47) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXReplaceImageHandles.cpp74 case NVPTX::SULD_1D_I8_CLAMP_R: in suldRegisterToIndexOpcode()
75 return NVPTX::SULD_1D_I8_CLAMP_I; in suldRegisterToIndexOpcode()
76 case NVPTX::SULD_1D_I16_CLAMP_R: in suldRegisterToIndexOpcode()
77 return NVPTX::SULD_1D_I16_CLAMP_I; in suldRegisterToIndexOpcode()
78 case NVPTX::SULD_1D_I32_CLAMP_R: in suldRegisterToIndexOpcode()
79 return NVPTX::SULD_1D_I32_CLAMP_I; in suldRegisterToIndexOpcode()
80 case NVPTX::SULD_1D_I64_CLAMP_R: in suldRegisterToIndexOpcode()
81 return NVPTX::SULD_1D_I64_CLAMP_I; in suldRegisterToIndexOpcode()
82 case NVPTX::SULD_1D_ARRAY_I8_CLAMP_R: in suldRegisterToIndexOpcode()
83 return NVPTX::SULD_1D_ARRAY_I8_CLAMP_I; in suldRegisterToIndexOpcode()
[all …]
H A DNVPTXISelDAGToDAG.cpp69 NVPTX::DivPrecisionLevel
205 (enablePack ? NVPTX::TCGEN05_LD_##SHAPE##_##NUM##_PACK \
206 : NVPTX::TCGEN05_LD_##SHAPE##_##NUM)
367 using NVPTX::PTXCmpMode::CmpMode; in getPTXCmpMode()
415 NVPTX::SETP_f16x2rr, DL, MVT::i1, MVT::i1, in SelectSETP_F16X2()
426 NVPTX::SETP_bf16x2rr, DL, MVT::i1, MVT::i1, in SelectSETP_BF16X2()
438 CurDAG->getMachineNode(NVPTX::I64toV2I32, SDLoc(N), EltVT, EltVT, Vector); in tryUNPACK_VECTOR()
450 if (!(NVPTX::isPackedVectorTy(VT) && VT.getVectorNumElements() == 2)) in tryEXTRACT_VECTOR_ELEMENT()
455 Opcode = NVPTX::I32toV2I16; in tryEXTRACT_VECTOR_ELEMENT()
457 Opcode = NVPTX::I64toV2I32; in tryEXTRACT_VECTOR_ELEMENT()
[all …]
H A DNVPTXRegisterInfo.cpp28 if (RC == &NVPTX::B128RegClass) in getNVPTXRegClassName()
30 if (RC == &NVPTX::B64RegClass) in getNVPTXRegClassName()
50 if (RC == &NVPTX::B32RegClass) in getNVPTXRegClassName()
52 if (RC == &NVPTX::B16RegClass) in getNVPTXRegClassName()
54 if (RC == &NVPTX::B1RegClass) in getNVPTXRegClassName()
56 if (RC == &NVPTX::SpecialRegsRegClass) in getNVPTXRegClassName()
62 if (RC == &NVPTX::B128RegClass) in getNVPTXRegClassStr()
64 if (RC == &NVPTX::B64RegClass) in getNVPTXRegClassStr()
66 if (RC == &NVPTX::B32RegClass) in getNVPTXRegClassStr()
68 if (RC == &NVPTX::B16RegClass) in getNVPTXRegClassStr()
[all …]
H A DNVPTXForwardParams.cpp56 case NVPTX::LD_i16: in traverseMoveUse()
57 case NVPTX::LD_i32: in traverseMoveUse()
58 case NVPTX::LD_i64: in traverseMoveUse()
59 case NVPTX::LD_i8: in traverseMoveUse()
60 case NVPTX::LDV_i16_v2: in traverseMoveUse()
61 case NVPTX::LDV_i16_v4: in traverseMoveUse()
62 case NVPTX::LDV_i32_v2: in traverseMoveUse()
63 case NVPTX::LDV_i32_v4: in traverseMoveUse()
64 case NVPTX::LDV_i64_v2: in traverseMoveUse()
65 case NVPTX::LDV_i64_v4: in traverseMoveUse()
[all …]
H A DNVPTXInstrInfo.cpp42 if (DestRC == &NVPTX::B1RegClass) { in copyPhysReg()
43 Op = NVPTX::IMOV1r; in copyPhysReg()
44 } else if (DestRC == &NVPTX::B16RegClass) { in copyPhysReg()
45 Op = NVPTX::MOV16r; in copyPhysReg()
46 } else if (DestRC == &NVPTX::B32RegClass) { in copyPhysReg()
47 Op = NVPTX::IMOV32r; in copyPhysReg()
48 } else if (DestRC == &NVPTX::B64RegClass) { in copyPhysReg()
49 Op = NVPTX::IMOV64r; in copyPhysReg()
50 } else if (DestRC == &NVPTX::B128RegClass) { in copyPhysReg()
51 Op = NVPTX::IMOV128r; in copyPhysReg()
[all …]
H A DNVPTXISelDAGToDAG.h33 NVPTX::Scope operator[](SyncScope::ID ID) const;
37 SmallMapVector<SyncScope::ID, NVPTX::Scope, 8> Scopes{};
46 NVPTX::DivPrecisionLevel getDivF32Level(const SDNode *N) const;
114 std::pair<NVPTX::Ordering, NVPTX::Scope>
116 NVPTX::Scope getOperationScope(MemSDNode *N, NVPTX::Ordering O) const;
H A DNVPTXFrameLowering.cpp54 (Is64Bit ? NVPTX::cvta_local_64 : NVPTX::cvta_local); in emitPrologue()
56 (Is64Bit ? NVPTX::MOV_DEPOT_ADDR_64 : NVPTX::MOV_DEPOT_ADDR); in emitPrologue()
77 FrameReg = NVPTX::VRDepot; in getFrameIndexReference()
H A DNVPTXProxyRegErasure.cpp61 case NVPTX::ProxyRegB1: in runOnMachineFunction()
62 case NVPTX::ProxyRegB16: in runOnMachineFunction()
63 case NVPTX::ProxyRegB32: in runOnMachineFunction()
64 case NVPTX::ProxyRegB64: { in runOnMachineFunction()
H A DNVPTXInstrFormats.td1 //===- NVPTXInstrFormats.td - NVPTX Instruction Formats-------*- tblgen -*-===//
10 // Describe NVPTX instructions format
20 // Generic NVPTX Format
26 let Namespace = "NVPTX";
H A DNVPTXRegisterInfo.td1 //===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
14 let Namespace = "NVPTX";
18 : RegisterClass <"NVPTX", regTypes, alignment, regList>;
58 // NVPTX::packed_types() in NVPTXUtilities.h accordingly!
67 // 128-bit regs are not defined as general regs in NVPTX. They are used for inlineASM only.
H A DNVPTXPeephole.cpp73 if (Root.getOpcode() != NVPTX::cvta_to_local_64 && in isCVTAToLocalCombinationCandidate()
74 Root.getOpcode() != NVPTX::cvta_to_local) in isCVTAToLocalCombinationCandidate()
86 (GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi64 && in isCVTAToLocalCombinationCandidate()
87 GenericAddrDef->getOpcode() != NVPTX::LEA_ADDRi)) { in isCVTAToLocalCombinationCandidate()
H A DNVPTXAssignValidGlobalNames.cpp52 GV.setName(NVPTX::getValidPTXIdentifier(GV.getName())); in runOnModule()
59 F.setName(NVPTX::getValidPTXIdentifier(F.getName())); in runOnModule()
H A DNVPTX.td1 //===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen -*-==//
8 // This is the top level entry point for the NVPTX target.
36 // NVPTX Architecture Hierarchy and Ordering:
106 // NVPTX supported processors.
152 def NVPTX : Target {
H A DNVPTXPassRegistry.def1 //===- NVPTXPassRegistry.def - Registry of NVPTX passes ---------*- C++ -*-===//
10 // NVPTX backend.
H A DNVPTXTargetMachine.h28 NVPTX::DrvInterface drvInterface;
47 NVPTX::DrvInterface getDrvInterface() const { return drvInterface; } in getDrvInterface()
H A DNVPTXISelLowering.cpp90 static cl::opt<NVPTX::DivPrecisionLevel> UsePrecDivF32(
95 clEnumValN(NVPTX::DivPrecisionLevel::Approx, "0", "Use div.approx"),
96 clEnumValN(NVPTX::DivPrecisionLevel::Full, "1", "Use div.full"),
97 clEnumValN(NVPTX::DivPrecisionLevel::IEEE754, "2",
99 clEnumValN(NVPTX::DivPrecisionLevel::IEEE754_NoFTZ, "3",
101 cl::init(NVPTX::DivPrecisionLevel::IEEE754));
121 NVPTX::DivPrecisionLevel
130 return NVPTX::DivPrecisionLevel::Approx; in getDivF32Level()
134 return NVPTX::DivPrecisionLevel::Approx; in getDivF32Level()
136 return NVPTX::DivPrecisionLevel::IEEE754; in getDivF32Level()
[all …]
H A DNVPTXAsmPrinter.cpp156 if (MI->getOpcode() == NVPTX::CALL_PROTOTYPE) { in lowerToMCInst()
218 if (RC == &NVPTX::B1RegClass) { in encodeVirtualRegister()
220 } else if (RC == &NVPTX::B16RegClass) { in encodeVirtualRegister()
222 } else if (RC == &NVPTX::B32RegClass) { in encodeVirtualRegister()
224 } else if (RC == &NVPTX::B64RegClass) { in encodeVirtualRegister()
226 } else if (RC == &NVPTX::B128RegClass) { in encodeVirtualRegister()
736 if (NTM.getDrvInterface() == NVPTX::NVCL) in emitHeader()
804 if (static_cast<NVPTXTargetMachine &>(TM).getDrvInterface() == NVPTX::CUDA) { in emitLinkageDirective()
1899 if (MO.getReg() == NVPTX::VRDepot) in printOperand()
H A DNVPTXTargetMachine.cpp155 drvInterface = NVPTX::NVCL; in NVPTXTargetMachine()
157 drvInterface = NVPTX::CUDA; in NVPTXTargetMachine()
H A DNVPTXUtilities.h93 namespace NVPTX {
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DNVPTX.cpp38 case NVPTX::BI__hmma_m16n16k16_ld_a: in getNVPTXMmaLdstInfo()
40 case NVPTX::BI__hmma_m16n16k16_ld_b: in getNVPTXMmaLdstInfo()
42 case NVPTX::BI__hmma_m16n16k16_ld_c_f16: in getNVPTXMmaLdstInfo()
44 case NVPTX::BI__hmma_m16n16k16_ld_c_f32: in getNVPTXMmaLdstInfo()
46 case NVPTX::BI__hmma_m32n8k16_ld_a: in getNVPTXMmaLdstInfo()
48 case NVPTX::BI__hmma_m32n8k16_ld_b: in getNVPTXMmaLdstInfo()
50 case NVPTX::BI__hmma_m32n8k16_ld_c_f16: in getNVPTXMmaLdstInfo()
52 case NVPTX::BI__hmma_m32n8k16_ld_c_f32: in getNVPTXMmaLdstInfo()
54 case NVPTX::BI__hmma_m8n32k16_ld_a: in getNVPTXMmaLdstInfo()
56 case NVPTX::BI__hmma_m8n32k16_ld_b: in getNVPTXMmaLdstInfo()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/MCTargetDesc/
H A DNVPTXInstPrinter.cpp105 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) in printCvtMode()
110 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) in printCvtMode()
115 if (Imm & NVPTX::PTXCvtMode::RELU_FLAG) in printCvtMode()
120 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { in printCvtMode()
123 case NVPTX::PTXCvtMode::NONE: in printCvtMode()
125 case NVPTX::PTXCvtMode::RNI: in printCvtMode()
128 case NVPTX::PTXCvtMode::RZI: in printCvtMode()
131 case NVPTX::PTXCvtMode::RMI: in printCvtMode()
134 case NVPTX::PTXCvtMode::RPI: in printCvtMode()
137 case NVPTX::PTXCvtMode::RN: in printCvtMode()
[all …]
H A DNVPTXTargetStreamer.cpp147 Streamer.emitRawText(NVPTX::getValidPTXIdentifier(SymName)); in emitValue()
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaNVPTX.cpp25 case NVPTX::BI__nvvm_cp_async_ca_shared_global_4: in CheckNVPTXBuiltinFunctionCall()
26 case NVPTX::BI__nvvm_cp_async_ca_shared_global_8: in CheckNVPTXBuiltinFunctionCall()
27 case NVPTX::BI__nvvm_cp_async_ca_shared_global_16: in CheckNVPTXBuiltinFunctionCall()
28 case NVPTX::BI__nvvm_cp_async_cg_shared_global_16: in CheckNVPTXBuiltinFunctionCall()
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DCuda.cpp382 void NVPTX::Assembler::ConstructJob(Compilation &C, const JobAction &JA, in ConstructJob()
528 void NVPTX::FatBinary::ConstructJob(Compilation &C, const JobAction &JA, in ConstructJob()
579 void NVPTX::Linker::ConstructJob(Compilation &C, const JobAction &JA, in ConstructJob()
666 void NVPTX::getNVPTXTargetFeatures(const Driver &D, const llvm::Triple &Triple, in getNVPTXTargetFeatures()
978 return new tools::NVPTX::Assembler(*this); in buildAssembler()
982 return new tools::NVPTX::Linker(*this); in buildLinker()
986 return new tools::NVPTX::Assembler(*this); in buildAssembler()
990 return new tools::NVPTX::FatBinary(*this); in buildLinker()
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DTargetBuiltins.h124 namespace NVPTX {
474 PPC::LastTSBuiltin, NVPTX::LastTSBuiltin, AMDGPU::LastTSBuiltin,

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