Lines Matching refs:NVPTX
479 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass); in NVPTXTargetLowering()
480 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
481 addRegisterClass(MVT::v2i16, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
482 addRegisterClass(MVT::v4i8, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
483 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
484 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass); in NVPTXTargetLowering()
485 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass); in NVPTXTargetLowering()
486 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass); in NVPTXTargetLowering()
487 addRegisterClass(MVT::f16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
488 addRegisterClass(MVT::v2f16, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
489 addRegisterClass(MVT::bf16, &NVPTX::Int16RegsRegClass); in NVPTXTargetLowering()
490 addRegisterClass(MVT::v2bf16, &NVPTX::Int32RegsRegClass); in NVPTXTargetLowering()
2422 DAG.getConstant(NVPTX::PTXPrmtMode::NONE, DL, MVT::i32)); in LowerVECTOR_SHUFFLE()
5232 return std::make_pair(0U, &NVPTX::Int1RegsRegClass); in getRegForInlineAsmConstraint()
5234 return std::make_pair(0U, &NVPTX::Int16RegsRegClass); in getRegForInlineAsmConstraint()
5236 return std::make_pair(0U, &NVPTX::Int16RegsRegClass); in getRegForInlineAsmConstraint()
5238 return std::make_pair(0U, &NVPTX::Int32RegsRegClass); in getRegForInlineAsmConstraint()
5241 return std::make_pair(0U, &NVPTX::Int64RegsRegClass); in getRegForInlineAsmConstraint()
5246 return std::make_pair(0U, &NVPTX::Int128RegsRegClass); in getRegForInlineAsmConstraint()
5249 return std::make_pair(0U, &NVPTX::Float32RegsRegClass); in getRegForInlineAsmConstraint()
5251 return std::make_pair(0U, &NVPTX::Float64RegsRegClass); in getRegForInlineAsmConstraint()
5531 if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) { in PerformANDCombine()