| /freebsd/contrib/llvm-project/llvm/lib/Support/ |
| H A D | CachePruning.cpp | 111 uint64_t Mult = 1; in parseCachePruningPolicy() local
114 Mult = 1024; in parseCachePruningPolicy()
118 Mult = 1024 * 1024; in parseCachePruningPolicy()
122 Mult = 1024 * 1024 * 1024; in parseCachePruningPolicy()
130 Policy.MaxSizeBytes = Size * Mult; in parseCachePruningPolicy()
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | cpsw.txt | 41 Mult and shift will be calculated basing on CPTS
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| H A D | keystone-netcp.txt | 120 Mult and shift will be calculated basing on CPTS
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 492 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); in LowerOperation()
494 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); in LowerOperation()
496 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); in LowerOperation()
1312 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped, in lowerMulDiv() local
1317 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); in lowerMulDiv()
1319 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); in lowerMulDiv()
1607 return lowerDSPIntr(Op, DAG, MipsISD::Mult); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsISelLowering.h | 133 Mult, enumerator
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| H A D | MipsISelLowering.cpp | 202 case MipsISD::Mult: return "MipsISD::Mult"; in getTargetNodeName()
1068 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL in performMADD_MSUBCombine() local
1078 if (!Mult.hasOneUse()) in performMADD_MSUBCombine()
1086 SDValue MultLHS = Mult->getOperand(0); in performMADD_MSUBCombine()
1087 SDValue MultRHS = Mult->getOperand(1); in performMADD_MSUBCombine()
1110 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), in performMADD_MSUBCombine()
1111 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; in performMADD_MSUBCombine()
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| H A D | MipsInstrInfo.td | 103 // Mult nodes.
104 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
1692 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
2352 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
2354 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
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| H A D | MicroMipsInstrInfo.td | 764 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
766 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
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| H A D | Mips64InstrInfo.td | 308 def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
310 def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedA53.td | 48 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 332 PermNetwork(ArrayRef<ElemType> Ord, unsigned Mult = 1) { in PermNetwork()
342 Row.resize(Mult*Log, None); in PermNetwork()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ScalarEvolution.cpp | 3383 const SCEV *Mult = getMulExpr(UDiv, RHS, SCEV::FlagNUW); in getURemExpr() local
3384 return getMinusSCEV(LHS, Mult, SCEV::FlagNUW); in getURemExpr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 49396 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial() argument
49398 DAG.getConstant(Mult, DL, VT)); in combineMulSpecial()
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