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Searched refs:MemVT (Results 1 – 25 of 42) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h1585 EVT MemVT, MachineMemOperand *MMO, ISD::LoadExtType ETy)
1586 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
2515 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2517 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2549 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2551 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2577 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2579 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2608 ISD::MemIndexedMode AM, EVT MemVT,
2610 : MemSDNode(NodeTy, Order, DL, VTs, MemVT, MMO) {
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H A DTargetLowering.h701 virtual bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, in storeOfVectorConstantIsCheap() argument
710 virtual bool mergeStoresAfterLegalization(EVT MemVT) const { in mergeStoresAfterLegalization() argument
715 virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, in canMergeStoresTo() argument
1470 EVT MemVT) const { in getLoadExtAction() argument
1471 if (ValVT.isExtended() || MemVT.isExtended()) return Expand; in getLoadExtAction()
1473 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction()
1481 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
1482 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
1487 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegalOrCustom() argument
1488 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
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H A DSelectionDAG.h1374 LLVM_ABI SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,
1381 LLVM_ABI SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
1387 LLVM_ABI SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
1393 EVT MemVT, EVT VT, SDValue Chain, SDValue Ptr,
1402 EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
1410 EVT MemVT, MachinePointerInfo PtrInfo,
1417 return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
1418 Alignment.value_or(getEVTAlign(MemVT)), Flags,
1424 EVT MemVT, MachineMemOperand *MMO);
1457 SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT,
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.h49 bool canMergeStoresTo(unsigned AS, EVT MemVT,
57 bool canCombineTruncStore(EVT ValVT, EVT MemVT, in canCombineTruncStore() argument
63 return isTruncStoreLegal(ValVT, MemVT); in canCombineTruncStore()
H A DR600ISelLowering.cpp1043 EVT MemVT = Store->getMemoryVT(); in lowerPrivateTruncStore() local
1076 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1117 EVT MemVT = StoreNode->getMemoryVT(); in LowerSTORE() local
1133 NewChain, DL, Value, Ptr, StoreNode->getPointerInfo(), MemVT, in LowerSTORE()
1143 if (Alignment < MemVT.getStoreSize() && in LowerSTORE()
1144 !allowsMisalignedMemoryAccesses(MemVT, AS, Alignment, in LowerSTORE()
1159 if (MemVT == MVT::i8) { in LowerSTORE()
1162 assert(MemVT == MVT::i16); in LowerSTORE()
1190 Op->getVTList(), Args, MemVT, in LowerSTORE()
1210 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
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H A DSIISelLowering.h52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
129 ArrayRef<SDValue> Ops, EVT MemVT,
143 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
184 EVT MemVT,
337 bool canMergeStoresTo(unsigned AS, EVT MemVT,
H A DAMDGPUISelLowering.cpp200 for (auto MemVT : in AMDGPUTargetLowering()
202 setLoadExtAction({ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD}, VT, MemVT, in AMDGPUTargetLowering()
977 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, in storeOfVectorConstantIsCheap() argument
1253 EVT MemVT = ArgVT; in analyzeFormalArgumentsCompute() local
1262 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1264 MemVT = ArgVT; in analyzeFormalArgumentsCompute()
1272 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1277 MemVT = ArgVT.getScalarType(); in analyzeFormalArgumentsCompute()
1280 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
1285 MemVT = EVT::getIntegerVT(State.getContext(), MemoryBits); in analyzeFormalArgumentsCompute()
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H A DSIISelLowering.cpp1789 bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT, in canMergeStoresTo() argument
1792 return (MemVT.getSizeInBits() <= 4 * 32); in canMergeStoresTo()
1795 return (MemVT.getSizeInBits() <= MaxPrivateBits); in canMergeStoresTo()
1798 return (MemVT.getSizeInBits() <= 2 * 32); in canMergeStoresTo()
2117 SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT, in convertArgType() argument
2123 VT.getVectorNumElements() != MemVT.getVectorNumElements()) { in convertArgType()
2125 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(), in convertArgType()
2132 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) && VT.bitsLT(MemVT)) { in convertArgType()
2134 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT)); in convertArgType()
2137 if (MemVT.isFloatingPoint()) in convertArgType()
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H A DAMDGPUISelLowering.h227 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT,
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp1369 EVT MemVT = LdNode->getMemoryVT(); in lowerLoadI1() local
1370 if (MemVT == MVT::v256i1 || MemVT == MVT::v4i64) { in lowerLoadI1()
1372 SDNode *VM = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MemVT); in lowerLoadI1()
1391 } else if (MemVT == MVT::v512i1 || MemVT == MVT::v8i64) { in lowerLoadI1()
1393 SDNode *VM = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MemVT); in lowerLoadI1()
1420 EVT MemVT = LdNode->getMemoryVT(); in lowerLOAD() local
1423 if (Subtarget->enableVPU() && MemVT.isVector() && !isMaskType(MemVT)) in lowerLOAD()
1433 if (MemVT == MVT::f128) in lowerLOAD()
1435 if (isMaskType(MemVT)) in lowerLOAD()
1493 EVT MemVT = StNode->getMemoryVT(); in lowerStoreI1() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp3964 EVT MemVT = cast<MemSDNode>(Op)->getMemoryVT(); in computeKnownBits() local
3965 KnownBits Known0(MemVT.getScalarSizeInBits()); in computeKnownBits()
9213 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, in getAtomic() argument
9219 ID.AddInteger(MemVT.getRawBits()); in getAtomic()
9221 dl.getIROrder(), Opcode, VTList, MemVT, MMO, ExtType)); in getAtomic()
9232 VTList, MemVT, MMO, ExtType); in getAtomic()
9243 EVT MemVT, SDVTList VTs, SDValue Chain, in getAtomicCmpSwap() argument
9251 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO); in getAtomicCmpSwap()
9254 SDValue SelectionDAG::getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, in getAtomic() argument
9279 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO); in getAtomic()
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H A DDAGCombiner.cpp763 EVT &MemVT, unsigned ShAmt = 0);
788 EVT MemVT, unsigned NumStores,
820 EVT MemVT, SDNode *Root, bool AllowVectors);
827 unsigned NumConsecutiveStores, EVT MemVT,
833 unsigned NumConsecutiveStores, EVT MemVT,
1490 EVT MemVT = LD->getMemoryVT(); in PromoteOperand() local
1496 MemVT, LD->getMemOperand()); in PromoteOperand()
1727 EVT MemVT = LD->getMemoryVT(); in PromoteLoad() local
1732 MemVT, LD->getMemOperand()); in PromoteLoad()
6840 ISD::LoadExtType ExtType, EVT &MemVT, in isLegalNarrowLdSt() argument
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H A DLegalizeVectorTypes.cpp1406 void DAGTypeLegalizer::IncrementPointer(MemSDNode *N, EVT MemVT, in IncrementPointer() argument
1410 unsigned IncrementSize = MemVT.getSizeInBits().getKnownMinValue() / 8; in IncrementPointer()
1412 if (MemVT.isScalableVector()) { in IncrementPointer()
3181 EVT MemVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), in SplitVecRes_VP_REVERSE() local
3183 SDValue StackPtr = DAG.CreateStackTemporary(MemVT.getStoreSize(), Alignment); in SplitVecRes_VP_REVERSE()
3208 EVL, MemVT, StoreMMO, ISD::UNINDEXED); in SplitVecRes_VP_REVERSE()
3233 EVT MemVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), in SplitVecRes_VP_SPLICE() local
3235 SDValue StackPtr = DAG.CreateStackTemporary(MemVT.getStoreSize(), Alignment); in SplitVecRes_VP_SPLICE()
4585 EVT MemVT = HG->getMemoryVT(); in SplitVecOp_VECTOR_HISTOGRAM() local
4593 SDValue Lo = DAG.getMaskedHistogram(DAG.getVTList(MVT::Other), MemVT, DL, in SplitVecOp_VECTOR_HISTOGRAM()
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H A DSelectionDAGBuilder.cpp2872 EVT MemVT = TLI.getMemValueType(DAG.getDataLayout(), CB.CmpLHS->getType()); in visitSwitchCase() local
2891 if (CondLHS.getValueType() != MemVT) { in visitSwitchCase()
2892 CondLHS = DAG.getPtrExtOrTrunc(CondLHS, getCurSDLoc(), MemVT); in visitSwitchCase()
2893 CondRHS = DAG.getPtrExtOrTrunc(CondRHS, getCurSDLoc(), MemVT); in visitSwitchCase()
3697 EVT MemVT = in visitICmp() local
3703 if (Op1.getValueType() != MemVT) { in visitICmp()
3704 Op1 = DAG.getPtrExtOrTrunc(Op1, getCurSDLoc(), MemVT); in visitICmp()
3705 Op2 = DAG.getPtrExtOrTrunc(Op2, getCurSDLoc(), MemVT); in visitICmp()
5134 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType(); in visitAtomicCmpXchg() local
5135 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other); in visitAtomicCmpXchg()
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H A DLegalizeDAG.cpp510 EVT MemVT = ST->getMemoryVT(); in LegalizeStoreOps() local
512 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT, in LegalizeStoreOps()
621 EVT MemVT = ST->getMemoryVT(); in LegalizeStoreOps() local
624 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT, in LegalizeStoreOps()
681 EVT MemVT = LD->getMemoryVT(); in LegalizeLoadOps() local
685 if (!TLI.allowsMemoryAccessForAlignment(*DAG.getContext(), DL, MemVT, in LegalizeLoadOps()
876 EVT MemVT = LD->getMemoryVT(); in LegalizeLoadOps() local
878 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, in LegalizeLoadOps()
1582 EVT MemVT = isa<BuildVectorSDNode>(Node) ? VT.getVectorElementType() in ExpandVectorBuildThroughStack() local
1592 unsigned TypeByteSize = MemVT.getSizeInBits() / 8; in ExpandVectorBuildThroughStack()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1190 bool mergeStoresAfterLegalization(EVT MemVT) const override { in mergeStoresAfterLegalization() argument
1191 return !MemVT.isVector(); in mergeStoresAfterLegalization()
1194 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
1556 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, in storeOfVectorConstantIsCheap() argument
H A DX86ISelDAGToDAG.cpp1427 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG() local
1428 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT); in PreprocessISelDAG()
1437 CurDAG->getEntryNode(), dl, N->getOperand(0), MemTmp, MPI, MemVT); in PreprocessISelDAG()
1439 MemTmp, MPI, MemVT); in PreprocessISelDAG()
1483 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG() local
1484 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT); in PreprocessISelDAG()
1497 Store = CurDAG->getMemIntrinsicNode(X86ISD::FST, dl, VTs, Ops, MemVT, in PreprocessISelDAG()
1506 assert(SrcVT == MemVT && "Unexpected VT!"); in PreprocessISelDAG()
1515 X86ISD::FLD, dl, VTs, Ops, MemVT, MPI, in PreprocessISelDAG()
1523 assert(DstVT == MemVT && "Unexpected VT!"); in PreprocessISelDAG()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp6492 EVT MemVT = MGT->getMemoryVT(); in LowerMGATHER() local
6501 DAG.getMaskedGather(MGT->getVTList(), MemVT, DL, Ops, in LowerMGATHER()
6513 if (IsScaled && ScaleVal != MemVT.getScalarStoreSize()) { in LowerMGATHER()
6521 return DAG.getMaskedGather(MGT->getVTList(), MemVT, DL, Ops, in LowerMGATHER()
6532 MemVT = MemVT.changeVectorElementTypeToInteger(); in LowerMGATHER()
6554 MemVT = ContainerVT.changeVectorElementType(MemVT.getVectorElementType()); in LowerMGATHER()
6563 DAG.getMaskedGather(DAG.getVTList(ContainerVT, MVT::Other), MemVT, DL, in LowerMGATHER()
6591 EVT MemVT = MSC->getMemoryVT(); in LowerMSCATTER() local
6601 if (IsScaled && ScaleVal != MemVT.getScalarStoreSize()) { in LowerMSCATTER()
6609 return DAG.getMaskedScatter(MSC->getVTList(), MemVT, DL, Ops, in LowerMSCATTER()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1412 EVT MemVT = StoreNode->getMemoryVT(); in tryFoldLoadStoreIntoMemOperand() local
1422 if (MemVT == MVT::i32) in tryFoldLoadStoreIntoMemOperand()
1424 else if (MemVT == MVT::i64) in tryFoldLoadStoreIntoMemOperand()
1433 if (MemVT == MVT::i32) in tryFoldLoadStoreIntoMemOperand()
1435 else if (MemVT == MVT::i64) in tryFoldLoadStoreIntoMemOperand()
1457 Operand = CurDAG->getTargetConstant(OperandV, DL, MemVT); in tryFoldLoadStoreIntoMemOperand()
H A DSystemZISelLowering.cpp5138 EVT MemVT = Node->getMemoryVT(); in lowerATOMIC_LOAD_SUB() local
5139 if (MemVT == MVT::i32 || MemVT == MVT::i64) { in lowerATOMIC_LOAD_SUB()
5141 assert(Op.getValueType() == MemVT && "Mismatched VTs"); in lowerATOMIC_LOAD_SUB()
5147 DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT), Src2); in lowerATOMIC_LOAD_SUB()
5148 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT, in lowerATOMIC_LOAD_SUB()
8096 EVT MemVT = SN->getMemoryVT(); in combineSTORE() local
8115 if (MemVT.isInteger() && SN->isTruncatingStore()) { in combineSTORE()
8117 combineTruncateExtract(SDLoc(N), MemVT, SN->getValue(), DCI)) { in combineSTORE()
8143 Ops, MemVT, SN->getMemOperand()); in combineSTORE()
8159 Ops, MemVT, SN->getMemOperand()); in combineSTORE()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp1097 const MVT MemVT = MemEVT.getSimpleVT(); in tryLoadVector() local
1117 const unsigned TotalWidth = MemVT.getSizeInBits(); in tryLoadVector()
1453 EVT MemVT = Mem->getMemoryVT(); in tryLoadParam() local
1461 Opcode = pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, in tryLoadParam()
1467 pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, NVPTX::LoadParamMemV2I8, in tryLoadParam()
1472 Opcode = pickOpcodeForVT(MemVT.getSimpleVT().SimpleTy, in tryLoadParam()
H A DNVPTXISelLowering.cpp3115 EVT MemVT = Load->getMemoryVT(); in LowerLOAD() local
3117 MemVT, *Load->getMemOperand())) { in LowerLOAD()
3179 const EVT MemVT = N->getMemoryVT(); in LowerSTOREVector() local
3183 if (ValVT != MemVT) in LowerSTOREVector()
5017 EVT MemVT = LD->getMemoryVT(); in combineUnpackingMovIntoLoad() local
5064 Operands, MemVT, LD->getMemOperand()); in combineUnpackingMovIntoLoad()
5106 EVT MemVT = ElementVT.getVectorElementType(); in combinePackingMovIntoStore() local
5115 MemVT = ST->getMemoryVT(); in combinePackingMovIntoStore()
5125 MemVT = ST->getMemoryVT(); in combinePackingMovIntoStore()
5177 MemVT, ST->getMemOperand()); in combinePackingMovIntoStore()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h710 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, in canMergeStoresTo() argument
713 return (MemVT.getSizeInBits() <= 32); in canMergeStoresTo()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2841 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); in createLoadLR() local
2851 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, in createLoadLR()
2858 EVT MemVT = LD->getMemoryVT(); in lowerLOAD() local
2864 if ((LD->getAlign().value() >= (MemVT.getSizeInBits() / 8)) || in lowerLOAD()
2865 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) in lowerLOAD()
2923 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); in createStoreLR() local
2932 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT, in createStoreLR()
2984 EVT MemVT = SD->getMemoryVT(); in lowerSTORE() local
2988 (SD->getAlign().value() < (MemVT.getSizeInBits() / 8)) && in lowerSTORE()
2989 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) in lowerSTORE()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3027 EVT MemVT = LD->getMemoryVT(); in usePartialVectorLoads() local
3028 if (!MemVT.isSimple()) in usePartialVectorLoads()
3030 switch(MemVT.getSimpleVT().SimpleTy) { in usePartialVectorLoads()
8602 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT, in canReuseLoadAddress() argument
8626 if (LD->getMemoryVT() != MemVT) in canReuseLoadAddress()
9574 EVT MemVT = InputNode->getMemoryVT(); in isValidSplatLoad() local
9580 (MemVT == Ty.getVectorElementType())) in isValidSplatLoad()
9586 if (MemVT == MVT::i32) { in isValidSplatLoad()
11608 EVT MemVT = AtomicNode->getMemoryVT(); in LowerATOMIC_CMP_SWAP() local
11609 if (MemVT.getSizeInBits() >= 32) in LowerATOMIC_CMP_SWAP()
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