Lines Matching refs:MemVT

1677 bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,  in canMergeStoresTo()  argument
1680 return (MemVT.getSizeInBits() <= 4 * 32); in canMergeStoresTo()
1683 return (MemVT.getSizeInBits() <= MaxPrivateBits); in canMergeStoresTo()
1686 return (MemVT.getSizeInBits() <= 2 * 32); in canMergeStoresTo()
2009 SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT, in convertArgType() argument
2015 VT.getVectorNumElements() != MemVT.getVectorNumElements()) { in convertArgType()
2017 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(), in convertArgType()
2025 VT.bitsLT(MemVT)) { in convertArgType()
2027 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT)); in convertArgType()
2030 if (MemVT.isFloatingPoint()) in convertArgType()
2041 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain, in lowerKernargMemParameter() argument
2049 if (MemVT.getStoreSize() < 4 && Alignment < 4) { in lowerKernargMemParameter()
2054 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter()
2067 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal); in lowerKernargMemParameter()
2068 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg); in lowerKernargMemParameter()
2075 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Alignment, in lowerKernargMemParameter()
2079 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg); in lowerKernargMemParameter()
2106 MVT MemVT = VA.getValVT(); in lowerStackParameter() local
2112 MemVT = VA.getLocVT(); in lowerStackParameter()
2128 MemVT); in lowerStackParameter()
2929 EVT MemVT = VA.getLocVT(); in LowerFormalArguments() local
2951 if (MemVT.getStoreSize() < 4 && Alignment < 4) { in LowerFormalArguments()
2955 EVT IntVT = MemVT.changeTypeToInteger(); in LowerFormalArguments()
2971 ArgVal = DAG.getNode(ISD::BITCAST, DL, MemVT, ArgVal); in LowerFormalArguments()
2972 NewArg = convertArgType(DAG, VT, MemVT, DL, ArgVal, in LowerFormalArguments()
3017 EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()); in LowerFormalArguments()
3018 if (MemVT.bitsLT(NewArg.getSimpleValueType())) in LowerFormalArguments()
3021 NewArg = DAG.getBitcast(MemVT, NewArg); in LowerFormalArguments()
3022 NewArg = convertArgType(DAG, VT, MemVT, DL, NewArg, in LowerFormalArguments()
3028 lowerKernargMemParameter(DAG, VT, MemVT, DL, Chain, Offset, in LowerFormalArguments()
8805 EVT MemVT = VData.getValueType(); in lowerRawBufferAtomicIntrin() local
8806 return DAG.getMemIntrinsicNode(NewOpcode, DL, Op->getVTList(), Ops, MemVT, in lowerRawBufferAtomicIntrin()
8833 EVT MemVT = VData.getValueType(); in lowerStructBufferAtomicIntrin() local
8834 return DAG.getMemIntrinsicNode(NewOpcode, DL, Op->getVTList(), Ops, MemVT, in lowerStructBufferAtomicIntrin()
9358 ArrayRef<SDValue> Ops, EVT MemVT, in getMemIntrinsicNode() argument
9392 EVT WidenedMemVT = EVT::getVectorVT(C, MemVT.getVectorElementType(), 4); in getMemIntrinsicNode()
9402 return DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops, MemVT, MMO); in getMemIntrinsicNode()
10189 EVT MemVT = Ld->getMemoryVT(); in widenLoad() local
10190 if ((MemVT.isSimple() && !DCI.isAfterLegalizeDAG()) || in widenLoad()
10191 MemVT.getSizeInBits() >= 32) in widenLoad()
10196 assert((!MemVT.isVector() || Ld->getExtensionType() == ISD::NON_EXTLOAD) && in widenLoad()
10207 EVT TruncVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits()); in widenLoad()
10208 if (MemVT.isFloatingPoint()) { in widenLoad()
10211 TruncVT = MemVT.changeTypeToInteger(); in widenLoad()
10253 EVT MemVT = Load->getMemoryVT(); in LowerLOAD() local
10255 if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) { in LowerLOAD()
10256 if (MemVT == MVT::i16 && isTypeLegal(MVT::i16)) in LowerLOAD()
10266 EVT RealMemVT = (MemVT == MVT::i1) ? MVT::i8 : MVT::i16; in LowerLOAD()
10271 if (!MemVT.isVector()) { in LowerLOAD()
10273 DAG.getNode(ISD::TRUNCATE, DL, MemVT, NewLD), in LowerLOAD()
10281 for (unsigned I = 0, N = MemVT.getVectorNumElements(); I != N; ++I) { in LowerLOAD()
10289 DAG.getBuildVector(MemVT, DL, Elts), in LowerLOAD()
10296 if (!MemVT.isVector()) in LowerLOAD()
10305 Alignment.value() < MemVT.getStoreSize() && MemVT.getSizeInBits() > 32) { in LowerLOAD()
10318 unsigned NumElements = MemVT.getVectorNumElements(); in LowerLOAD()
10323 if (MemVT.isPow2VectorType() || in LowerLOAD()
10340 if (MemVT.isPow2VectorType() || in LowerLOAD()
10392 if (allowsMisalignedMemoryAccessesImpl(MemVT.getSizeInBits(), AS, in LowerLOAD()
10397 if (MemVT.isVector()) in LowerLOAD()
10402 MemVT, *Load->getMemOperand())) { in LowerLOAD()
11304 EVT MemVT, in performSHLPtrCombine() argument
11332 Type *Ty = MemVT.getTypeForEVT(*DCI.DAG.getContext()); in performSHLPtrCombine()
12075 auto MemVT = L->getMemoryVT(); in isExtendedFrom16Bits() local
12076 return !MemVT.isVector() && MemVT.getSizeInBits() == 16; in isExtendedFrom16Bits()