| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSERegisterInfo.cpp | 200 bool IsKill = false; in eliminateFI() local
235 IsKill = true; in eliminateFI()
252 IsKill = true; in eliminateFI()
256 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFI()
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| H A D | Mips16RegisterInfo.cpp | 123 bool IsKill = false; in eliminateFI() local
139 IsKill = true; in eliminateFI()
141 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaRegisterInfo.cpp | 98 bool IsKill = false; in eliminateFrameIndex() local
121 IsKill = true; in eliminateFrameIndex()
124 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFrameIndex()
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| H A D | XtensaFrameLowering.cpp | 212 bool IsKill = !IsA0AndRetAddrIsTaken; in spillCalleeSavedRegisters() local
214 TII.storeRegToStackSlot(EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), in spillCalleeSavedRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | FixupStatepointCallerSaved.cpp | 112 bool &IsKill, const TargetInstrInfo &TII, in performCopyPropagation() argument
117 IsKill = false; in performCopyPropagation()
154 IsKill = DestSrc->Source->isKill(); in performCopyPropagation()
161 } else if (IsKill) { in performCopyPropagation()
418 bool IsKill = true; in spillRegisters() local
420 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI); in spillRegisters()
424 TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI, in spillRegisters()
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| H A D | ScheduleDAGInstrs.cpp | 412 bool IsKill = MO.getSubReg() == 0 || MO.isUndef(); in addVRegDefDeps() local
416 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask; in addVRegDefDeps()
1118 bool IsKill = LiveRegs.available(Reg); in toggleKills() local
1121 MO.setIsKill(IsKill && !MRI.isReserved(Reg)); in toggleKills()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrBuilder.h | 50 bool IsKill, int Offset) { in addRegIndirectWithDisp() argument
51 return MIB.addImm(Offset).addReg(Reg, getKillRegState(IsKill)); in addRegIndirectWithDisp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 126 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
136 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
141 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 84 bool IsKill; member
120 bool IsKill, int Index, RegScavenger *RS) in SGPRSpillBuilder()
121 : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()), in SGPRSpillBuilder()
1216 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
1240 .addReg(Src, getKillRegState(IsKill)); in spillVGPRtoAGPR()
1248 .addReg(Src, getKillRegState(IsKill)); in spillVGPRtoAGPR()
1331 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1554 SrcDstRegState |= getKillRegState(IsKill); in buildSpillLoadStore()
1579 auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill); in buildSpillLoadStore()
1624 .addReg(SubReg, getKillRegState(IsKill)); in buildSpillLoadStore()
[all …]
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| H A D | SIShrinkInstructions.cpp | 335 bool IsKill = NewAddrDwords == Info->VAddrDwords; in shrinkMIMG() local
357 IsKill = false; in shrinkMIMG()
390 MI.getOperand(VAddr0Idx).setIsKill(IsKill); in shrinkMIMG()
558 const bool IsKill = SrcReg->isKill(); in shrinkScalarLogicOp() local
565 /*isImp*/ false, IsKill, in shrinkScalarLogicOp()
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| H A D | SIOptimizeExecMaskingPreRA.cpp | 247 bool IsKill = SelLI->Query(CmpIdx.getRegSlot()).isKill(); in optimizeVcndVcmpPair() local
250 if (MRI->use_nodbg_empty(SelReg) && (IsKill || IsDead)) { in optimizeVcndVcmpPair()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 1418 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg); in insertCSRSpillsInBlock() local
1421 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI, Register()); in insertCSRSpillsInBlock()
1422 if (IsKill) in insertCSRSpillsInBlock()
1749 bool IsKill = MI->getOperand(2).isKill(); in expandStoreInt() local
1758 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1812 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVecPred() local
1827 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1901 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVec2() local
1916 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
1927 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
[all …]
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| H A D | HexagonBlockRanges.cpp | 325 bool IsKill = Op.isKill(); in computeInitialLiveRanges() local
328 if (IsKill) in computeInitialLiveRanges()
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| H A D | HexagonFrameLowering.h | 177 bool IsDef, bool IsKill) const;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 275 unsigned Dst, unsigned Src, bool IsKill) { in insertCopy() argument
278 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.h | 45 bool IsKill, int FrameIndex,
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| H A D | CSKYInstrInfo.cpp | 393 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
429 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.h | 72 bool IsKill, int FrameIndex,
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| H A D | ARCInstrInfo.cpp | 295 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, in storeRegToStackSlot() argument
314 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.h | 38 bool IsKill, int FrameIndex,
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| H A D | LoongArchFrameLowering.cpp | 444 bool IsKill = in spillCalleeSavedRegisters() local
447 TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, CS.getFrameIdx(), RC, TRI, in spillCalleeSavedRegisters()
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| H A D | LoongArchInstrInfo.cpp | 112 bool IsKill, int FI, const TargetRegisterClass *RC, in storeRegToStackSlot() argument
140 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 56 Register SourceRegister, bool IsKill, int FrameIndex,
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| H A D | LanaiInstrInfo.cpp | 51 Register SourceRegister, bool IsKill, int FrameIndex, in storeRegToStackSlot() argument
63 .addReg(SourceRegister, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /freebsd/contrib/llvm-project/llvm/lib/Support/Unix/ |
| H A D | Signals.inc | 304 enum class SignalKind { IsKill, IsInfo };
313 case SignalKind::IsKill:
331 registerHandler(S, SignalKind::IsKill);
333 registerHandler(S, SignalKind::IsKill);
335 registerHandler(SIGPIPE, SignalKind::IsKill);
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