| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSERegisterInfo.cpp | 196 bool IsKill = false; in eliminateFI() local
231 IsKill = true; in eliminateFI()
248 IsKill = true; in eliminateFI()
252 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFI()
|
| H A D | Mips16RegisterInfo.cpp | 114 bool IsKill = false; in eliminateFI() local
130 IsKill = true; in eliminateFI()
132 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFI()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaRegisterInfo.cpp | 102 bool IsKill = false; in eliminateFrameIndex() local
125 IsKill = true; in eliminateFrameIndex()
128 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFrameIndex()
|
| H A D | XtensaFrameLowering.cpp | 314 bool IsKill = !IsA0AndRetAddrIsTaken; in spillCalleeSavedRegisters() local
316 TII.storeRegToStackSlot(EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(), in spillCalleeSavedRegisters()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | FixupStatepointCallerSaved.cpp | 117 bool &IsKill, const TargetInstrInfo &TII, in performCopyPropagation() argument
122 IsKill = false; in performCopyPropagation()
159 IsKill = DestSrc->Source->isKill(); in performCopyPropagation()
166 } else if (IsKill) { in performCopyPropagation()
416 bool IsKill = true; in spillRegisters() local
418 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI); in spillRegisters()
422 TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI, in spillRegisters()
|
| H A D | ScheduleDAGInstrs.cpp | 433 bool IsKill = MO.getSubReg() == 0 || MO.isUndef(); in addVRegDefDeps() local
437 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask; in addVRegDefDeps()
1135 bool IsKill = LiveRegs.available(Reg); in toggleKills() local
1138 MO.setIsKill(IsKill && !MRI.isReserved(Reg)); in toggleKills()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrBuilder.h | 50 bool IsKill, int Offset) { in addRegIndirectWithDisp() argument
51 return MIB.addImm(Offset).addReg(Reg, getKillRegState(IsKill)); in addRegIndirectWithDisp()
|
| H A D | M68kInstrInfo.h | 283 bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 127 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
138 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
143 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 1405 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg); in insertCSRSpillsInBlock() local
1408 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI, Register()); in insertCSRSpillsInBlock()
1409 if (IsKill) in insertCSRSpillsInBlock()
1736 bool IsKill = MI->getOperand(2).isKill(); in expandStoreInt() local
1745 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1799 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVecPred() local
1814 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1888 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVec2() local
1903 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
1914 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
[all …]
|
| H A D | HexagonBlockRanges.cpp | 324 bool IsKill = Op.isKill(); in computeInitialLiveRanges() local
327 if (IsKill) in computeInitialLiveRanges()
|
| H A D | HexagonFrameLowering.h | 179 bool IsDef, bool IsKill) const;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 273 unsigned Dst, unsigned Src, bool IsKill) { in insertCopy() argument
276 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.h | 45 bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
|
| H A D | CSKYInstrInfo.cpp | 393 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
430 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.h | 73 bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
|
| H A D | ARCInstrInfo.cpp | 296 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, in storeRegToStackSlot() argument
316 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 90 bool IsKill; member
126 bool IsKill, int Index, RegScavenger *RS) in SGPRSpillBuilder()
127 : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()), in SGPRSpillBuilder()
1452 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
1476 .addReg(Src, getKillRegState(IsKill)); in spillVGPRtoAGPR()
1484 .addReg(Src, getKillRegState(IsKill)); in spillVGPRtoAGPR()
1571 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1799 SrcDstRegState |= getKillRegState(IsKill); in buildSpillLoadStore()
1824 auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill); in buildSpillLoadStore()
1869 .addReg(SubReg, getKillRegState(IsKill)); in buildSpillLoadStore()
[all …]
|
| H A D | SIShrinkInstructions.cpp | 346 bool IsKill = NewAddrDwords == Info->VAddrDwords; in shrinkMIMG() local
368 IsKill = false; in shrinkMIMG()
401 MI.getOperand(VAddr0Idx).setIsKill(IsKill); in shrinkMIMG()
586 const bool IsKill = SrcReg->isKill(); in shrinkScalarLogicOp() local
593 /*isImp*/ false, IsKill, in shrinkScalarLogicOp()
|
| H A D | SIOptimizeExecMaskingPreRA.cpp | 255 bool IsKill = SelLI->Query(CmpIdx.getRegSlot()).isKill(); in optimizeVcndVcmpPair() local
258 if (MRI->use_nodbg_empty(SelReg) && (IsKill || IsDead)) { in optimizeVcndVcmpPair()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchInstrInfo.h | 39 bool IsKill, int FrameIndex, const TargetRegisterClass *RC,
|
| H A D | LoongArchFrameLowering.cpp | 449 bool IsKill = in spillCalleeSavedRegisters() local
452 TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, CS.getFrameIdx(), RC, TRI, in spillCalleeSavedRegisters()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 58 Register SourceRegister, bool IsKill, int FrameIndex,
|
| H A D | LanaiInstrInfo.cpp | 49 Register SourceRegister, bool IsKill, int FrameIndex, in storeRegToStackSlot() argument
62 .addReg(SourceRegister, getKillRegState(IsKill)) in storeRegToStackSlot()
|
| /freebsd/contrib/llvm-project/llvm/lib/Support/Unix/ |
| H A D | Signals.inc | 310 enum class SignalKind { IsKill, IsInfo };
319 case SignalKind::IsKill:
337 registerHandler(S, SignalKind::IsKill);
339 registerHandler(S, SignalKind::IsKill);
341 registerHandler(SIGPIPE, SignalKind::IsKill);
|