1349cc55cSDimitry Andric //===-- CSKYInstrInfo.h - CSKY Instruction Information --------*- C++ -*---===// 2349cc55cSDimitry Andric // 3349cc55cSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4349cc55cSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5349cc55cSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6349cc55cSDimitry Andric // 7349cc55cSDimitry Andric //===----------------------------------------------------------------------===// 8349cc55cSDimitry Andric // 9349cc55cSDimitry Andric // This file contains the CSKY implementation of the TargetInstrInfo class. 10349cc55cSDimitry Andric // 11349cc55cSDimitry Andric //===----------------------------------------------------------------------===// 12349cc55cSDimitry Andric 13349cc55cSDimitry Andric #ifndef LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H 14349cc55cSDimitry Andric #define LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H 15349cc55cSDimitry Andric 16349cc55cSDimitry Andric #include "MCTargetDesc/CSKYMCTargetDesc.h" 17349cc55cSDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 18349cc55cSDimitry Andric 19349cc55cSDimitry Andric #define GET_INSTRINFO_HEADER 20349cc55cSDimitry Andric #include "CSKYGenInstrInfo.inc" 21349cc55cSDimitry Andric 22349cc55cSDimitry Andric namespace llvm { 23349cc55cSDimitry Andric 24349cc55cSDimitry Andric class CSKYSubtarget; 25349cc55cSDimitry Andric 26349cc55cSDimitry Andric class CSKYInstrInfo : public CSKYGenInstrInfo { 2704eeddc0SDimitry Andric bool v2sf; 2804eeddc0SDimitry Andric bool v2df; 2904eeddc0SDimitry Andric bool v3sf; 3004eeddc0SDimitry Andric bool v3df; 3104eeddc0SDimitry Andric 32349cc55cSDimitry Andric protected: 33349cc55cSDimitry Andric const CSKYSubtarget &STI; 34349cc55cSDimitry Andric 35349cc55cSDimitry Andric public: 36349cc55cSDimitry Andric explicit CSKYInstrInfo(CSKYSubtarget &STI); 370eae32dcSDimitry Andric 38*0fca6ea1SDimitry Andric Register isLoadFromStackSlot(const MachineInstr &MI, 390eae32dcSDimitry Andric int &FrameIndex) const override; 40*0fca6ea1SDimitry Andric Register isStoreToStackSlot(const MachineInstr &MI, 410eae32dcSDimitry Andric int &FrameIndex) const override; 420eae32dcSDimitry Andric 430eae32dcSDimitry Andric void storeRegToStackSlot(MachineBasicBlock &MBB, 440eae32dcSDimitry Andric MachineBasicBlock::iterator MI, Register SrcReg, 450eae32dcSDimitry Andric bool IsKill, int FrameIndex, 460eae32dcSDimitry Andric const TargetRegisterClass *RC, 47bdd1243dSDimitry Andric const TargetRegisterInfo *TRI, 48bdd1243dSDimitry Andric Register VReg) const override; 490eae32dcSDimitry Andric 500eae32dcSDimitry Andric void loadRegFromStackSlot(MachineBasicBlock &MBB, 510eae32dcSDimitry Andric MachineBasicBlock::iterator MI, Register DestReg, 520eae32dcSDimitry Andric int FrameIndex, const TargetRegisterClass *RC, 53bdd1243dSDimitry Andric const TargetRegisterInfo *TRI, 54bdd1243dSDimitry Andric Register VReg) const override; 550eae32dcSDimitry Andric 560eae32dcSDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 570eae32dcSDimitry Andric const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 580eae32dcSDimitry Andric bool KillSrc) const override; 590eae32dcSDimitry Andric 6004eeddc0SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 6104eeddc0SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 6204eeddc0SDimitry Andric const DebugLoc &DL, 6304eeddc0SDimitry Andric int *BytesAdded = nullptr) const override; 6404eeddc0SDimitry Andric 6504eeddc0SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 6604eeddc0SDimitry Andric MachineBasicBlock *&FBB, 6704eeddc0SDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 6804eeddc0SDimitry Andric bool AllowModify = false) const override; 6904eeddc0SDimitry Andric 7004eeddc0SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 7104eeddc0SDimitry Andric int *BytesRemoved = nullptr) const override; 7204eeddc0SDimitry Andric 7304eeddc0SDimitry Andric bool 7404eeddc0SDimitry Andric reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 7504eeddc0SDimitry Andric 7604eeddc0SDimitry Andric MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 7704eeddc0SDimitry Andric 7804eeddc0SDimitry Andric unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 7904eeddc0SDimitry Andric 8004eeddc0SDimitry Andric Register getGlobalBaseReg(MachineFunction &MF) const; 8104eeddc0SDimitry Andric 820eae32dcSDimitry Andric // Materializes the given integer Val into DstReg. 830eae32dcSDimitry Andric Register movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 8481ad6265SDimitry Andric const DebugLoc &DL, uint64_t Val, 850eae32dcSDimitry Andric MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; 86349cc55cSDimitry Andric }; 87349cc55cSDimitry Andric 88349cc55cSDimitry Andric } // namespace llvm 89349cc55cSDimitry Andric 90349cc55cSDimitry Andric #endif // LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H 91