10b57cec5SDimitry Andric //===- ARCInstrInfo.h - ARC Instruction Information -------------*- C++ -*-===// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric // 90b57cec5SDimitry Andric // This file contains the ARC implementation of the TargetInstrInfo class. 100b57cec5SDimitry Andric // 110b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 120b57cec5SDimitry Andric 130b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H 140b57cec5SDimitry Andric #define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric #include "ARCRegisterInfo.h" 170b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 180b57cec5SDimitry Andric 190b57cec5SDimitry Andric #define GET_INSTRINFO_HEADER 200b57cec5SDimitry Andric #include "ARCGenInstrInfo.inc" 210b57cec5SDimitry Andric 220b57cec5SDimitry Andric namespace llvm { 230b57cec5SDimitry Andric 240b57cec5SDimitry Andric class ARCSubtarget; 250b57cec5SDimitry Andric 260b57cec5SDimitry Andric class ARCInstrInfo : public ARCGenInstrInfo { 270b57cec5SDimitry Andric const ARCRegisterInfo RI; 280b57cec5SDimitry Andric virtual void anchor(); 290b57cec5SDimitry Andric 300b57cec5SDimitry Andric public: 31349cc55cSDimitry Andric ARCInstrInfo(const ARCSubtarget &); 320b57cec5SDimitry Andric getRegisterInfo()330b57cec5SDimitry Andric const ARCRegisterInfo &getRegisterInfo() const { return RI; } 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric /// If the specified machine instruction is a direct 360b57cec5SDimitry Andric /// load from a stack slot, return the virtual or physical register number of 370b57cec5SDimitry Andric /// the destination along with the FrameIndex of the loaded stack slot. If 380b57cec5SDimitry Andric /// not, return 0. This predicate must return 0 if the instruction has 390b57cec5SDimitry Andric /// any side effects other than loading from the stack slot. 40*0fca6ea1SDimitry Andric Register isLoadFromStackSlot(const MachineInstr &MI, 410b57cec5SDimitry Andric int &FrameIndex) const override; 420b57cec5SDimitry Andric 430b57cec5SDimitry Andric /// If the specified machine instruction is a direct 440b57cec5SDimitry Andric /// store to a stack slot, return the virtual or physical register number of 450b57cec5SDimitry Andric /// the source reg along with the FrameIndex of the loaded stack slot. If 460b57cec5SDimitry Andric /// not, return 0. This predicate must return 0 if the instruction has 470b57cec5SDimitry Andric /// any side effects other than storing to the stack slot. 48*0fca6ea1SDimitry Andric Register isStoreToStackSlot(const MachineInstr &MI, 490b57cec5SDimitry Andric int &FrameIndex) const override; 500b57cec5SDimitry Andric 510b57cec5SDimitry Andric unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 520b57cec5SDimitry Andric 530b57cec5SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 540b57cec5SDimitry Andric MachineBasicBlock *&FBB, 550b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 560b57cec5SDimitry Andric bool AllowModify) const override; 570b57cec5SDimitry Andric 580b57cec5SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 590b57cec5SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 60349cc55cSDimitry Andric const DebugLoc &, 610b57cec5SDimitry Andric int *BytesAdded = nullptr) const override; 620b57cec5SDimitry Andric 630b57cec5SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 640b57cec5SDimitry Andric int *BytesRemoved = nullptr) const override; 650b57cec5SDimitry Andric 660b57cec5SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 67349cc55cSDimitry Andric const DebugLoc &, MCRegister DestReg, MCRegister SrcReg, 680b57cec5SDimitry Andric bool KillSrc) const override; 690b57cec5SDimitry Andric 700b57cec5SDimitry Andric void storeRegToStackSlot(MachineBasicBlock &MBB, 715ffd83dbSDimitry Andric MachineBasicBlock::iterator MI, Register SrcReg, 72349cc55cSDimitry Andric bool IsKill, int FrameIndex, 730b57cec5SDimitry Andric const TargetRegisterClass *RC, 74bdd1243dSDimitry Andric const TargetRegisterInfo *TRI, 75bdd1243dSDimitry Andric Register VReg) const override; 760b57cec5SDimitry Andric 770b57cec5SDimitry Andric void loadRegFromStackSlot(MachineBasicBlock &MBB, 785ffd83dbSDimitry Andric MachineBasicBlock::iterator MI, Register DestReg, 790b57cec5SDimitry Andric int FrameIndex, const TargetRegisterClass *RC, 80bdd1243dSDimitry Andric const TargetRegisterInfo *TRI, 81bdd1243dSDimitry Andric Register VReg) const override; 820b57cec5SDimitry Andric 830b57cec5SDimitry Andric bool 840b57cec5SDimitry Andric reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 850b57cec5SDimitry Andric 860b57cec5SDimitry Andric 870b57cec5SDimitry Andric bool isPostIncrement(const MachineInstr &MI) const override; 880b57cec5SDimitry Andric 890b57cec5SDimitry Andric // ARC-specific 900b57cec5SDimitry Andric bool isPreIncrement(const MachineInstr &MI) const; 910b57cec5SDimitry Andric 920b57cec5SDimitry Andric virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, 930b57cec5SDimitry Andric unsigned &BasePos, 940b57cec5SDimitry Andric unsigned &OffsetPos) const override; 950b57cec5SDimitry Andric 960b57cec5SDimitry Andric // Emit code before MBBI to load immediate value into physical register Reg. 970b57cec5SDimitry Andric // Returns an iterator to the new instruction. 980b57cec5SDimitry Andric MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, 990b57cec5SDimitry Andric MachineBasicBlock::iterator MI, 1000b57cec5SDimitry Andric unsigned Reg, uint64_t Value) const; 1010b57cec5SDimitry Andric }; 1020b57cec5SDimitry Andric 1030b57cec5SDimitry Andric } // end namespace llvm 1040b57cec5SDimitry Andric 1050b57cec5SDimitry Andric #endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H 106