| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorCombine.cpp | 199 AlignVectors(const HexagonVectorCombine &HVC_) : HVC(HVC_) {} in AlignVectors()
209 AddrInfo(const HexagonVectorCombine &HVC, Instruction *I, Value *A, Type *T, in AddrInfo()
212 NeedAlign(HVC.getTypeAlignment(ValTy)) {} in AddrInfo()
364 const HexagonVectorCombine &HVC; member in __anoncba317990111::AlignVectors
422 HvxIdioms(const HexagonVectorCombine &HVC_) : HVC(HVC_) { in HvxIdioms()
423 auto *Int32Ty = HVC.getIntTy(32); in HvxIdioms()
424 HvxI32Ty = HVC.getHvxTy(Int32Ty, /*Pair=*/false); in HvxIdioms()
425 HvxP32Ty = HVC.getHvxTy(Int32Ty, /*Pair=*/true); in HvxIdioms()
480 const HexagonVectorCombine &HVC; member in __anoncba317990111::HvxIdioms
624 return AddrInfo(HVC, L, L->getPointerOperand(), L->getType(), in getAddrInfo()
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| /freebsd/sys/contrib/device-tree/Bindings/arm/firmware/ |
| H A D | linaro,optee-tz.txt | 20 "hvc" : HVC #0, with the register assignments specified
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| H A D | sdei.txt | 34 * "hvc" : HVC #0, with the register assignments specified in this
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| /freebsd/sys/contrib/device-tree/Bindings/firmware/xilinx/ |
| H A D | xlnx,zynqmp-firmware.txt | 20 - "hvc" : HVC #0, following the SMCCC
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 706 case ARM::HVC: in isIndirectCall()
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| H A D | ARMScheduleA57.td | 119 "(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$",
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| H A D | ARMInstrInfo.td | 2804 def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary,
2809 // Even though HVC isn't predicable, it's encoding includes a condition field.
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| H A D | ARMInstrThumb2.td | 4303 // Alias for HVC without the ".w" optional width specifier
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| /freebsd/contrib/file/magic/Magdir/ |
| H A D | console | 86 >0x11 string *NINTENDO-HVC* Famicom Disk System disk image:
93 1 string *NINTENDO-HVC* Famicom Disk System disk image:
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedFalkorDetails.td | 1245 def : InstRW<[FalkorWr_1none_0cyc], (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, SVC)>;
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| H A D | AArch64SchedKryoDetails.td | 477 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
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| H A D | AArch64InstrInfo.td | 3209 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 721 case ARM::HVC: { in checkDecodedInstruction()
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