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Searched refs:GPR64RegClass (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
67 const MCRegisterClass *GPR64RegClass; variable
H A DMipsMachineFunction.cpp50 return Mips::GPR64RegClass; in getGlobalBaseRegClass()
82 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
162 ? Mips::GPR64RegClass in createEhDataRegsFI()
H A DMipsSERegisterInfo.cpp59 return &Mips::GPR64RegClass; in intRegClass()
223 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
H A DMipsSEInstrInfo.cpp149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. in copyPhysReg()
150 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg()
159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. in copyPhysReg()
226 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
304 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
598 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
H A DMipsSEFrameLowering.cpp422 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
719 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
895 Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
911 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; in determineCalleeSaves()
H A DMipsSubtarget.cpp232 CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass in getCriticalPathRCs()
H A DMipsRegisterInfo.cpp54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
H A DMipsSEISelLowering.cpp70 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()
3333 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3519 : &Mips::GPR64RegClass); in emitST_F16_PSEUDO()
3525 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass); in emitST_F16_PSEUDO()
3571 : &Mips::GPR64RegClass); in emitLD_F16_PSEUDO()
3663 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPROUND_PSEUDO()
3767 IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitFPEXTEND_PSEUDO()
H A DMipsISelLowering.cpp4158 return std::make_pair(0U, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
4182 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
4846 Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass); in emitLDR_D()
4981 Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass); in emitSTR_D()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIChecking.cpp109 const MCRegisterClass *GPR64RegClass = in hasLiveDefs() local
120 RegIsGPR64 = GPR64RegClass->contains(MO.getReg()); in hasLiveDefs()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp382 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
415 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
476 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
489 Register Result64 = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
1320 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()
1363 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()
1406 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()
1448 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()
1734 RC = &AArch64::GPR64RegClass; in emitLogicalOp_rs()
1836 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
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H A DAArch64SLSHardening.cpp200 assert(AArch64::GPR64RegClass.contains(Reg)); in indexOfXReg()
211 assert(AArch64::GPR64RegClass.getRegister(Result).id() == Reg && in indexOfXReg()
218 return AArch64::GPR64RegClass.getRegister(N); in xRegByIndex()
H A DAArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
110 return AArch64::GPR64RegClass.contains(Reg); in isGPR64()
H A DAArch64CleanupLocalDynamicTLSPass.cpp127 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
H A DAArch64FrameLowering.cpp372 if (AArch64::GPR64RegClass.contains(Reg)) in homogeneousPrologEpilog()
572 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateCallFramePseudoInstr()
1083 for (unsigned Reg : AArch64::GPR64RegClass) { in findScratchNonCalleeSaveRegister()
2986 if (AArch64::GPR64RegClass.contains(RPI.Reg1)) in computeCalleeSaveRegisterPairs()
3014 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()
3657 const bool RegIsGPR64 = AArch64::GPR64RegClass.contains(Reg); in determineCalleeSaves()
3672 if (RegIsGPR64 && !AArch64::GPR64RegClass.contains(PairedReg)) { in determineCalleeSaves()
3677 AArch64::GPR64RegClass.contains(Reg, PairedReg) || in determineCalleeSaves()
3682 if (AArch64::GPR64RegClass.contains(Reg) && in determineCalleeSaves()
3696 if (AArch64::GPR64RegClass.contains(PairedReg) && in determineCalleeSaves()
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H A DAArch64RegisterInfo.cpp567 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. in getCrossCopyRegClass()
881 MI.getMF()->getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in createScratchRegisterForInstruction()
973 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
H A DAArch64InstrInfo.cpp301 Register Scavenged = RS->FindUnusedReg(&AArch64::GPR64RegClass); in insertIndirectBranch()
838 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
839 RC = &AArch64::GPR64RegClass; in insertSelect()
2169 AArch64::GPR64RegClass.contains(DstReg)); in isGPRCopy()
3468 if (RC->hasSuperClassEq(&AArch64::GPR64RegClass)) { in emitLdStWithAddr()
4755 AArch64::GPR64RegClass.contains(SrcReg)) { in copyPhysReg()
4760 if (AArch64::GPR64RegClass.contains(DestReg) && in copyPhysReg()
4781 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy"); in copyPhysReg()
4790 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy"); in copyPhysReg()
4880 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in storeRegToStackSlot()
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H A DAArch64CollectLOH.cpp502 for (MCPhysReg Reg : AArch64::GPR64RegClass) in handleNormalInst()
H A DAArch64FalkorHWPFFix.cpp749 for (unsigned ScratchReg : AArch64::GPR64RegClass) { in runOnLoop()
H A DAArch64LoadStoreOptimizer.cpp1201 LdRt, AArch64::sub_32, &AArch64::GPR64RegClass)) in promoteLoadFromStore()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp78 if (GPR32RegClass->contains(SubReg) || GPR64RegClass->contains(SubReg)) in SetPhysRegUsed()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp579 : &AArch64::GPR64RegClass; in getRegClassForTypeOnBank()
623 : &AArch64::GPR64RegClass; in getMinClassForRegBank()
1608 TestReg, UseWReg ? AArch64::GPR32RegClass : AArch64::GPR64RegClass, in emitTestBit()
2005 Register ArgsAddrReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectVaStartDarwin()
2041 auto MovZ = MIB.buildInstr(AArch64::MOVZXi, {&AArch64::GPR64RegClass}, {}); in materializeLargeCMVal()
2052 : MRI.createVirtualRegister(&AArch64::GPR64RegClass); in materializeLargeCMVal()
2088 RBI.constrainGenericRegister(NewSrc, AArch64::GPR64RegClass, MRI); in preISelLower()
2115 MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass); in preISelLower()
2318 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in earlySelect()
2685 DefSize == 32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in select()
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H A DAArch64PostSelectOptimize.cpp223 TryMatchDUP(&AArch64::GPR64RegClass, &AArch64::FPR64RegClass, in foldCopyDup()
H A DAArch64LegalizerInfo.cpp1479 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
1501 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
2094 auto Scratch = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in legalizeAtomicCmpxchg128()
H A DAArch64CallLowering.cpp518 Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass); in handleMustTailForwardedRegisters()

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