382   const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass  in materializeInt()
415         &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in materializeFP()
476       ResultReg = createResultReg(&AArch64::GPR64RegClass);  in materializeGV()
489     Register Result64 = createResultReg(&AArch64::GPR64RegClass);  in materializeGV()
1320       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rr()
1363     RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_ri()
1406       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rs()
1448     RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitAddSub_rx()
1734     RC = &AArch64::GPR64RegClass;  in emitLogicalOp_rs()
1836              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1841              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1846              &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;  in emitLoad()
1850     RC = &AArch64::GPR64RegClass;  in emitLoad()
1878     Register Reg64 = createResultReg(&AArch64::GPR64RegClass);  in emitLoad()
2693     RC = &AArch64::GPR64RegClass;  in selectSelect()
2852       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);  in selectFPToInt()
2985       RC = &AArch64::GPR64RegClass;  in fastLowerArguments()
3257       CallReg = createResultReg(&AArch64::GPR64RegClass);  in fastLowerCall()
3450     Register SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in fastLowerIntrinsicCall()
3461       DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,  in fastLowerIntrinsicCall()
4028       Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in emiti1Ext()
4061       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitMul_rr()
4069   return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,  in emitSMULL_rr()
4077   return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,  in emitUMULL_rr()
4095       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSL_rr()
4120       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSL_ri()
4197       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSR_rr()
4223       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitLSR_ri()
4313       (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitASR_rr()
4339       Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitASR_ri()
4451     Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);  in emitIntExt()
4461       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitIntExt()
4548     Register Reg64 = createResultReg(&AArch64::GPR64RegClass);  in optimizeIntExtLoad()
4591         Register ResultReg = createResultReg(&AArch64::GPR64RegClass);  in selectIntExt()
4644       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in selectRem()
4834   case MVT::i64: RC = &AArch64::GPR64RegClass; break;  in selectBitCast()
4927     RC = &AArch64::GPR64RegClass;  in selectSDiv()
5066     ResRC = &AArch64::GPR64RegClass;  in selectAtomicCmpXchg()