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Searched refs:FSQRT (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3705 { ISD::FSQRT, MVT::f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3706 { ISD::FSQRT, MVT::v4f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3707 { ISD::FSQRT, MVT::v8f32, { 6, 12, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3708 { ISD::FSQRT, MVT::v16f32, { 12, 20, 1, 3 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3709 { ISD::FSQRT, MVT::f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3710 { ISD::FSQRT, MVT::v2f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3711 { ISD::FSQRT, MVT::v4f64, { 12, 18, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3712 { ISD::FSQRT, MVT::v8f64, { 24, 32, 1, 3 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3836 { ISD::FSQRT, MVT::f32, { 7, 15, 1, 1 } }, // vsqrtss in getIntrinsicInstrCost()
3837 { ISD::FSQRT, MVT::v4f32, { 7, 15, 1, 1 } }, // vsqrtps in getIntrinsicInstrCost()
[all …]
H A DX86IntrinsicsInfo.h1039 X86_INTRINSIC_DATA(avx512_sqrt_pd_512, INTR_TYPE_1OP, ISD::FSQRT,
1041 X86_INTRINSIC_DATA(avx512_sqrt_ps_512, INTR_TYPE_1OP, ISD::FSQRT,
1439 X86_INTRINSIC_DATA(avx512fp16_sqrt_ph_512, INTR_TYPE_1OP, ISD::FSQRT,
H A DX86.td605 // TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
607 // vector FSQRT has higher throughput than the corresponding NR code.
/freebsd/contrib/one-true-awk/
H A Dawk.h144 #define FSQRT 2 macro
H A Dlex.c89 { "sqrt", FSQRT, BLTIN },
H A Drun.c2092 case FSQRT: in bltin()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def102 DAG_FUNCTION(sqrt, 1, 1, experimental_constrained_sqrt, FSQRT)
H A DVPIntrinsics.def379 VP_PROPERTY_FUNCTIONAL_SDOPC(FSQRT)
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h960 FSQRT, enumerator
H A DBasicTTIImpl.h544 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
1971 ISD = ISD::FSQRT; in getTypeBasedIntrinsicInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td553 // FDIV,FSQRT
555 // TODO: Specialize FSQRT for longer latency.
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td122 defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
H A DMipsSEISelLowering.cpp147 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in MipsSETargetLowering()
392 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
1915 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
H A DMipsInstrFPU.td543 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td121 defm FSQRT : FT_XZ<0b011010, "fsqrt", UnOpFrag<(fsqrt node:$Src)>>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h93 FSQRT, enumerator
H A DP10InstrResources.td71 FSQRT,
H A DP9InstrResources.td1153 FSQRT
H A DPPCISelLowering.cpp444 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
449 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
855 setOperationAction(ISD::FSQRT, VT, Expand); in PPCTargetLowering()
953 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
1045 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
1282 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in PPCTargetLowering()
1689 case PPCISD::FSQRT: in getTargetNodeName()
13740 return DAG.getNode(PPCISD::FSQRT, SDLoc(Op), VT, Op); in getSqrtResultForDenormInput()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp207 case ISD::FSQRT: return "fsqrt"; in getOperationName()
H A DLegalizeFloatTypes.cpp141 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1465 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
2619 case ISD::FSQRT: in PromoteFloatResult()
3061 case ISD::FSQRT: in SoftPromoteHalfResult()
H A DLegalizeVectorOps.cpp401 case ISD::FSQRT: in LegalizeOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1899 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1924 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1976 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
3280 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp211 ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FSQRT, ISD::FCBRT, in SITargetLowering()
270 setOperationAction(ISD::FSQRT, {MVT::f32, MVT::f64}, Custom); in SITargetLowering()
478 setOperationAction(ISD::FSQRT, MVT::f16, Custom); in SITargetLowering()
5764 case ISD::FSQRT: { in LowerOperation()
6463 case ISD::FSQRT: { in ReplaceNodeResults()
12588 if ((VT == MVT::f16 && N0.getOpcode() == ISD::FSQRT) && in performRcpCombine()
12629 case ISD::FSQRT: in isCanonicalized()
14416 if (RHS.getOpcode() == ISD::FSQRT) { in performFDivCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1609 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1654 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()

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