| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 3886 { ISD::FSQRT, MVT::f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3887 { ISD::FSQRT, MVT::v4f32, { 3, 12, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3888 { ISD::FSQRT, MVT::v8f32, { 6, 12, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3889 { ISD::FSQRT, MVT::v16f32, { 12, 20, 1, 3 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3890 { ISD::FSQRT, MVT::f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3891 { ISD::FSQRT, MVT::v2f64, { 6, 18, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3892 { ISD::FSQRT, MVT::v4f64, { 12, 18, 1, 1 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
3893 { ISD::FSQRT, MVT::v8f64, { 24, 32, 1, 3 } }, // Skylake from http://www.agner.org/ in getIntrinsicInstrCost()
4045 { ISD::FSQRT, MVT::f32, { 7, 15, 1, 1 } }, // vsqrtss in getIntrinsicInstrCost()
4046 { ISD::FSQRT, MVT::v4f32, { 7, 15, 1, 1 } }, // vsqrtps in getIntrinsicInstrCost()
[all …]
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| H A D | X86IntrinsicsInfo.h | 1380 X86_INTRINSIC_DATA(avx512_sqrt_pd_512, INTR_TYPE_1OP, ISD::FSQRT,
1382 X86_INTRINSIC_DATA(avx512_sqrt_ps_512, INTR_TYPE_1OP, ISD::FSQRT,
1780 X86_INTRINSIC_DATA(avx512fp16_sqrt_ph_512, INTR_TYPE_1OP, ISD::FSQRT,
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| H A D | X86.td | 624 // TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
626 // vector FSQRT has higher throughput than the corresponding NR code.
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| /freebsd/contrib/one-true-awk/ |
| H A D | awk.h | 144 #define FSQRT 2 macro
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| H A D | lex.c | 89 { "sqrt", FSQRT, BLTIN },
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 103 DAG_FUNCTION(sqrt, 1, 1, experimental_constrained_sqrt, FSQRT)
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| H A D | VPIntrinsics.def | 352 VP_PROPERTY_FUNCTIONAL_SDOPC(FSQRT)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1004 FSQRT, enumerator
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| H A D | BasicTTIImpl.h | 641 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
2244 ISD = ISD::FSQRT; in getTypeBasedIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVSchedSyntacoreSCR7.td | 370 // - Non-pipelined FDIV/FSQRT
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| H A D | RISCVTargetTransformInfo.cpp | 1372 FsqrtType = TLI->getTypeToPromoteTo(ISD::FSQRT, FsqrtType); in getIntrinsicInstrCost()
1385 FsqrtType = TLI->getTypeToPromoteTo(ISD::FSQRT, FsqrtType); in getIntrinsicInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedCyclone.td | 553 // FDIV,FSQRT
555 // TODO: Specialize FSQRT for longer latency.
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCScheduleP7.td | 309 def : InstRW<[P7_ScalarFPU_44C, P7_DISP_FP], (instrs FSQRT, FSQRT_rec)>;
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| H A D | PPCISelLowering.h | 90 FSQRT, enumerator
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| H A D | P10InstrResources.td | 71 FSQRT,
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| H A D | P9InstrResources.td | 1155 FSQRT
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFPU.td | 122 defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
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| H A D | MipsSEISelLowering.cpp | 186 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in MipsSETargetLowering()
431 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
1959 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsInstrFPU.td | 543 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 216 setOperationAction(ISD::FSQRT, VT, Expand); in XtensaTargetLowering()
222 setOperationAction(ISD::FSQRT, VT, Expand); in XtensaTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfoF1.td | 121 defm FSQRT : FT_XZ<0b011010, "fsqrt", UnOpFrag<(fsqrt node:$Src)>>;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 219 case ISD::FSQRT: return "fsqrt"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 149 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1622 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
2853 case ISD::FSQRT: in PromoteFloatResult()
3339 case ISD::FSQRT: in SoftPromoteHalfResult()
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| H A D | LegalizeVectorOps.cpp | 414 case ISD::FSQRT: in LegalizeOp()
1306 case ISD::FSQRT: in Expand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1884 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1901 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1949 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
3140 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
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