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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td97 def MOVGR2FR_W : FP_MOV<0x0114a400, FPR32, GPR>;
98 def MOVFR2GR_S : FP_MOV<0x0114b400, GPR, FPR32>;
103 def MOVFR2CF_xS : FP_MOV<0x0114d000, CFR, FPR32>;
104 def MOVCF2FR_xS : FP_MOV<0x0114d400, FPR32, CFR>;
165 def : PatFprFpr<fadd, FADD_S, FPR32>;
166 def : PatFprFpr<fsub, FSUB_S, FPR32>;
167 def : PatFprFpr<fmul, FMUL_S, FPR32>;
168 def : PatFprFpr<fdiv, FDIV_S, FPR32>;
169 def : PatFprFpr<fcopysign, FCOPYSIGN_S, FPR32>;
170 def : PatFprFpr<fmaxnum_ieee, FMAX_S, FPR32>;
[all...]
H A DLoongArchFloat64InstrInfo.td69 def FFINT_S_L : FP_CONV<0x011d1800, FPR32, FPR64>;
70 def FTINT_L_S : FP_CONV<0x011b2400, FPR64, FPR32>;
71 def FTINTRM_L_S : FP_CONV<0x011a2400, FPR64, FPR32>;
72 def FTINTRP_L_S : FP_CONV<0x011a6400, FPR64, FPR32>;
73 def FTINTRZ_L_S : FP_CONV<0x011aa400, FPR64, FPR32>;
74 def FTINTRNE_L_S : FP_CONV<0x011ae400, FPR64, FPR32>;
75 def FCVT_S_D : FP_CONV<0x01191800, FPR32, FPR64>;
76 def FCVT_D_S : FP_CONV<0x01192400, FPR64, FPR32>;
77 def FFINT_D_W : FP_CONV<0x011d2000, FPR64, FPR32>;
79 def FTINT_W_D : FP_CONV<0x011b0800, FPR32, FPR6
[all...]
H A DLoongArchFloatInstrFormats.td19 // Some FP instructions are defined twice, for accepting FPR32 and FPR64, but
171 class FP_ALU_2R<bits<32> op, RegisterClass rc = FPR32>
174 class FP_ALU_3R<bits<32> op, RegisterClass rc = FPR32>
177 class FP_ALU_4R<bits<32> op, RegisterClass rc = FPR32>
183 class FP_CMP<bits<32> op, RegisterClass rc = FPR32>
186 class FP_CONV<bits<32> op, RegisterClass rcd = FPR32, RegisterClass rcs = FPR32>
189 class FP_MOV<bits<32> op, RegisterClass rcd = FPR32, RegisterClass rcs = FPR32>
192 class FP_SEL<bits<32> op, RegisterClass rc = FPR32>
205 class FP_LOAD_3R<bits<32> op, RegisterClass rc = FPR32>
208 class FP_LOAD_2RI12<bits<32> op, RegisterClass rc = FPR32>
[all …]
H A DLoongArchRegisterInfo.td170 def FPR32 : RegisterClass<"LoongArch", [f32], 32, (sequence "F%u", 0, 31)>;
H A DLoongArchLASXInstrInfo.td1553 def : Pat<(vector_insert v8f32:$vd, FPR32:$fj, uimm3:$imm),
1554 (XVINSGR2VR_W $vd, (COPY_TO_REGCLASS FPR32:$fj, GPR), uimm3:$imm)>;
1709 def : Pat<(lasxsplatf32 FPR32:$fj),
1710 (XVREPLVE0_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32))>;
H A DLoongArchLSXInstrInfo.td1673 def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, uimm2:$imm),
1674 (VINSGR2VR_W $vd, (COPY_TO_REGCLASS FPR32:$fj, GPR), uimm2:$imm)>;
1832 def : Pat<(lsxsplatf32 FPR32:$fj),
1833 (VREPLVEI_W (SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32), 0)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfa.td81 def FLI_S : FPFLI_r<0b1111000, 0b00001, 0b000, FPR32, "fli.s">,
85 def FMINM_S: FPALU_rr<0b0010100, 0b010, "fminm.s", FPR32, Commutable=1>;
86 def FMAXM_S: FPALU_rr<0b0010100, 0b011, "fmaxm.s", FPR32, Commutable=1>;
89 def FROUND_S : FPUnaryOp_r_frm<0b0100000, 0b00100, FPR32, FPR32, "fround.s">,
91 def FROUNDNX_S : FPUnaryOp_r_frm<0b0100000, 0b00101, FPR32, FPR32, "froundnx.s">,
95 def FLTQ_S : FPCmp_rr<0b1010000, 0b101, "fltq.s", FPR32>;
96 def FLEQ_S : FPCmp_rr<0b1010000, 0b100, "fleq.s", FPR32>;
168 (FLTQ_S GPR:$rd, FPR32
[all...]
H A DRISCVInstrInfoF.td113 def FExt : ExtInfo<"", "", [HasStdExtF], f32, FPR32, FPR32, ?, ?>;
296 def FLW : FPLoad_r<0b010, "flw", FPR32, WriteFLD32>;
301 def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
387 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">,
391 def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
399 def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
400 def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
402 def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
403 def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
404 def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
[all …]
H A DRISCVInstrInfoZfbfmin.td35 def FCVT_BF16_S : FPUnaryOp_r_frm<0b0100010, 0b01000, FPR16, FPR32, "fcvt.bf16.s">,
37 def FCVT_S_BF16 : FPUnaryOp_r_frm<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
54 def : Pat<(bf16 (riscv_fpround_bf16 FPR32:$rs1)),
55 (FCVT_BF16_S FPR32:$rs1, FRM_DYN)>;
H A DRISCVScheduleXSf.td29 foreach f = ["FPR16", "FPR32", "FPR64"] in {
53 foreach f = ["FPR16", "FPR32", "FPR64"] in {
H A DRISCVInstrInfoXSf.td110 !eq(TyRs1, FPR32): 0b101,
115 dag Ins = SwapVCIXIns<!if(!ne(TyRs1, FPR32), (ins uimm2:$funct6_lo2),
124 !if(!ne(TyRs1, FPR32), "$funct6_lo2, $rd, $rs2, $rs1",
152 if !eq(TyRs1, FPR32) then {
191 defm FV : CustomSiFiveVCIX<"fv", VCIX_XV, uimm5, VR, FPR32>, Sched<[]>;
195 defm FVV : CustomSiFiveVCIX<"fvv", VCIX_XVV, VR, VR, FPR32>, Sched<[]>;
199 defm FVW : CustomSiFiveVCIX<"fvw", VCIX_XVW, VR, VR, FPR32>, Sched<[]>;
405 FPR32, MxListW[i],
712 !eq(Sew, 32) : FPR32,
716 !eq(Scalar, f32) : "FPR32",
H A DRISCVInstrInfoZfh.td42 f16, FPR16, FPR32, ?, FPR16>;
44 f16, FPR16, FPR32, ?, FPR16>;
46 ?, ?, FPR32, FPR64, FPR16>;
48 ?, ?, FPR32, FPR64, FPR16>;
276 def : Pat<(f16 (fcopysign FPR16:$rs1, FPR32:$rs2)),
438 def : Pat<(f16 (any_fpround FPR32:$rs1)), (FCVT_H_S FPR32:$rs1, FRM_DYN)>;
446 def : Pat<(fcopysign FPR32:$rs1, (f16 FPR16:$rs2)), (FSGNJ_S $rs1, (FCVT_S_H $rs2, FRM_RNE))>;
H A DRISCVInstrInfoC.td522 def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
580 def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
733 def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32:$rd, SPMem:$rs1, 0)>;
734 def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32:$rs2, SPMem:$rs1, 0)>;
998 def : CompressPat<(FLW FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
999 (C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
1040 def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
1041 (C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
H A DRISCVInstrInfoD.td59 def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>;
245 def : Pat<(any_fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1, FRM_RNE)>;
286 def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2,
288 def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
H A DRISCVInstrInfoXTHead.td431 def TH_FLRW : THLoadIndexed<FPR32, 0b01000, "th.flrw">,
433 def TH_FSRW : THStoreIndexed<FPR32, 0b01000, "th.fsrw">,
447 def TH_FLURW : THLoadIndexed<FPR32, 0b01010, "th.flurw">,
449 def TH_FSURW : THStoreIndexed<FPR32, 0b01010, "th.fsurw">,
807 defm : StIdxPat<store, TH_FSRW, FPR32, f32>;
817 defm : StZextIdxPat<store, TH_FSURW, FPR32, f32>;
H A DRISCVInstrInfoV.td516 (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm),
523 (ins VR:$vd, FPR32:$rs1, VR:$vs2, VMaskOp:$vm),
1445 (ins VR:$vs2, FPR32:$rs1, VMV0:$v0),
1453 (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1">,
1649 def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
1654 (ins VR:$vd, FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">,
H A DRISCVRegisterInfo.td259 def FPR32 : RISCVRegisterClass<[f32], 32, (add
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td205 class FPR32<bits<16> num, string n> : SystemZReg<n> {
210 class FPR64<bits<16> num, string n, FPR32 high>
226 def F#I#S : FPR32<I, "f"#I>;
227 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
231 def F#I#S : FPR32<I, "v"#I>;
232 def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td4972 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
4973 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
4978 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
4979 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
5018 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
5020 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
5027 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
5029 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
5100 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
5116 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
[all …]
H A DAArch64InstrInfo.td1399 def : Pat<(bf16 (any_fpround (f32 FPR32:$Rn))), (BFCVT $Rn)>;
2241 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
4879 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
4889 def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>;
4919 FPR32))>;
5020 def : Pat<(f32 (OpNode (f32 FPR32:$Rn),
5023 FPR32:$Rn, (EXTRACT_SUBREG V128:$Rm, ssub))>;
5038 def : Pat<(fmul (fneg FPR32:$a), (f32 FPR32:$b)),
5039 (FNMULSrr FPR32:$a, FPR32:$b)>;
5076 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
[all …]
H A DAArch64SVEInstrInfo.td826 def : Pat<(nxv4f32 (splat_vector (f32 FPR32:$src))),
827 (DUP_ZZI_S (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$src, ssub), 0)>;
828 def : Pat<(nxv2f32 (splat_vector (f32 FPR32:$src))),
829 (DUP_ZZI_S (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$src, ssub), 0)>;
3168 def : Pat<(nxv16i8 (vector_insert (nxv16i8 (undef)), (i32 FPR32:$src), 0)),
3169 (INSERT_SUBREG (nxv16i8 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
3170 def : Pat<(nxv8i16 (vector_insert (nxv8i16 (undef)), (i32 FPR32:$src), 0)),
3171 (INSERT_SUBREG (nxv8i16 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
3172 def : Pat<(nxv4i32 (vector_insert (nxv4i32 (undef)), (i32 FPR32:$src), 0)),
3173 (INSERT_SUBREG (nxv4i32 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
[all …]
H A DAArch64RegisterInfo.td464 def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)> {
725 def FPR32Op : RegisterOperand<FPR32, "printOperand"> {
726 let ParserMatchClass = FPRAsmOperand<"FPR32">;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td18 let MIOperandInfo = (ops FPR32, uimm5);
29 def FPR32Op : RegisterOperand<FPR32, "printFPR">;
272 def : Pat<(sint_to_fp GPR:$vrx), (f2FS32TOF_S (COPY_TO_REGCLASS $vrx, FPR32))>, Requires<[HasFPUv3_SF]>;
273 def : Pat<(uint_to_fp GPR:$vrx), (f2FU32TOF_S (COPY_TO_REGCLASS $vrx, FPR32))>, Requires<[HasFPUv3_SF]>;
274 def : Pat<(sint_to_fp GPR:$vrx), (f2FS32TOF_D (COPY_TO_REGCLASS $vrx, FPR32))>, Requires<[HasFPUv3_DF]>;
275 def : Pat<(uint_to_fp GPR:$vrx), (f2FU32TOF_D (COPY_TO_REGCLASS $vrx, FPR32))>, Requires<[HasFPUv3_DF]>;
289 def : Pat<(f32 fpimm16:$imm),(COPY_TO_REGCLASS (MOVI32 (fpimm32_lo16 fpimm16:$imm)), FPR32)>,
291 def : Pat<(f32 fpimm16_16:$imm), (COPY_TO_REGCLASS (MOVIH32 (fpimm32_hi16 fpimm16_16:$imm)), FPR32)>,
293 def : Pat<(f32 fpimm:$imm),(COPY_TO_REGCLASS (ORI32 (MOVIH32 (fpimm32_hi16 fpimm:$imm)), (fpimm32_lo16 fpimm:$imm)), FPR32)>,
H A DCSKYRegisterInfo.td191 def FPR32 : RegisterClass<"CSKY", [f32], 32,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp323 const auto &FPR32 = AArch64MCRegisterClasses[AArch64::FPR32RegClassID]; in isFpOrNEON() local
331 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) || in isFpOrNEON()

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