| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 962 { ISD::FDIV, MVT::f64, { 4, 14, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
963 { ISD::FDIV, MVT::v2f64, { 4, 14, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
964 { ISD::FDIV, MVT::v4f64, { 8, 14, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
965 { ISD::FDIV, MVT::v8f64, { 16, 23, 1, 3 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
977 { ISD::FDIV, MVT::f32, { 3, 11, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
978 { ISD::FDIV, MVT::v4f32, { 3, 11, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
979 { ISD::FDIV, MVT::v8f32, { 5, 11, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
980 { ISD::FDIV, MVT::v16f32, { 10, 18, 1, 3 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1077 { ISD::FDIV, MVT::f32, { 18, 19, 1, 1 } }, // divss in getArithmeticInstrCost()
1078 { ISD::FDIV, MVT::v4f32, { 35, 36, 1, 1 } }, // divps in getArithmeticInstrCost()
[all …]
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| H A D | X86IntrinsicsInfo.h | 503 X86_INTRINSIC_DATA(avx512_div_pd_512, INTR_TYPE_2OP, ISD::FDIV,
505 X86_INTRINSIC_DATA(avx512_div_ps_512, INTR_TYPE_2OP, ISD::FDIV,
1172 X86_INTRINSIC_DATA(avx512fp16_div_ph_512, INTR_TYPE_2OP, ISD::FDIV,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 115 ADD_BINARY_VVP_OP_COMPACT(FDIV)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 55 DAG_INSTRUCTION(FDiv, 2, 1, experimental_constrained_fdiv, FDIV)
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| H A D | VPIntrinsics.def | 357 HELPER_REGISTER_BINARY_FP_VP(fdiv, VP_FDIV, FDiv, FDIV)
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 400 FDIV, enumerator
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| H A D | SDPatternMatch.h | 641 return BinaryOpc_match<LHS, RHS, false>(ISD::FDIV, L, R);
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| H A D | TargetLowering.h | 879 return N->getOpcode() == ISD::FDIV; in optimizeFMulOrFDivAsShiftAddBitcast()
2941 case ISD::FDIV: in isBinOp()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 559 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } in visitFDiv()
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| H A D | SelectionDAGDumper.cpp | 291 case ISD::FDIV: return "fdiv"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 94 case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break; in SoftenFloatResult()
1424 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break; in ExpandFloatResult()
2627 case ISD::FDIV: in PromoteFloatResult()
3069 case ISD::FDIV: in SoftPromoteHalfResult()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFPU.td | 36 defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,
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| H A D | MipsSEISelLowering.cpp | 131 setOperationAction(ISD::FDIV, MVT::f16, Promote); in MipsSETargetLowering()
386 setOperationAction(ISD::FDIV, Ty, Legal); in addMSAFloatType()
1862 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsInstrFPU.td | 672 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfoF1.td | 125 defm FDIV : FT_XYZ<0b011000, "fdiv", BinOpFrag<(fdiv node:$LHS, node:$RHS)>>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1898 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1923 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1975 setOperationAction(ISD::FDIV, MVT::f32, Promote); in SparcTargetLowering()
3278 case ISD::FDIV: return LowerF128Op(Op, DAG, in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1609 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1653 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
1788 setOperationAction(ISD::FDIV, MVT::f32, Custom); in HexagonTargetLowering()
3362 case ISD::FDIV: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 617 case ISD::FDIV: in getArithmeticInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedCyclone.td | 553 // FDIV,FSQRT
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| H A D | AArch64SchedA57.td | 474 // Note: These were simply duplicated from ASIMD FDIV because of missing documentation
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | P10InstrResources.td | 56 FDIV,
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| H A D | P9InstrResources.td | 1133 FDIV
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 1749 case ISD::FDIV: in getArithmeticInstrCost()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1782 case FDiv: return ISD::FDIV; in InstructionOpcodeToISD()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrArithmetic.td | 1108 defm FDIV : MxFBinaryOp<"div", 0b1100000, 0b1100100, 0b0100000>;
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