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Searched refs:DstReg (Results 1 – 25 of 153) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp59 Register DstReg) { in buildMI() argument
60 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg); in buildMI()
152 Register DstReg = MI.getOperand(0).getReg(); in expandArith() local
159 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandArith()
185 Register DstReg = MI.getOperand(0).getReg(); in expandLogic() local
192 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogic()
245 Register DstReg = MI.getOperand(0).getReg(); in expandLogicImm() local
252 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogicImm()
305 Register DstReg = MI.getOperand(0).getReg(); in expand() local
309 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
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H A DAVRRegisterInfo.cpp111 Register DstReg) { in foldFrameOffset() argument
122 if (DstReg != MI.getOperand(0).getReg()) { in foldFrameOffset()
167 Register DstReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
168 assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer"); in eliminateFrameIndex()
172 BuildMI(MBB, MI, dl, TII.get(AVR::MOVWRdRr), DstReg).addReg(AVR::R29R28); in eliminateFrameIndex()
175 splitReg(DstReg, DstLoReg, DstHiReg); in eliminateFrameIndex()
196 foldFrameOffset(II, Offset, DstReg); in eliminateFrameIndex()
199 switch (DstReg) { in eliminateFrameIndex()
217 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg) in eliminateFrameIndex()
218 .addReg(DstReg, RegState::Kill) in eliminateFrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp233 Register DstReg; in movImm() local
235 DstReg = MRI.createVirtualRegister(&CSKY::GPRRegClass); in movImm()
238 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI32), DstReg) in movImm()
242 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) in movImm()
246 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) in movImm()
249 BuildMI(MBB, MBBI, DL, get(CSKY::ORI32), DstReg) in movImm()
250 .addReg(DstReg) in movImm()
256 DstReg = MRI.createVirtualRegister(&CSKY::mGPRRegClass); in movImm()
258 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
262 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h67 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt() local
74 if (MRI.getType(DstReg) == MRI.getType(TruncSrc)) in tryCombineAnyExt()
75 replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs, in tryCombineAnyExt()
78 Builder.buildAnyExtOrTrunc(DstReg, TruncSrc); in tryCombineAnyExt()
79 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
91 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineAnyExt()
92 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
100 const LLT DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
109 DstReg, CstVal.getCImm()->getValue().sext(DstTy.getSizeInBits())); in tryCombineAnyExt()
110 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 MCRegister DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
205 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
221 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
242 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
252 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
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H A DHexagonMCCompound.cpp81 MCRegister DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
97 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
111 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
113 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
123 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
125 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getCompoundCandidateGroup()
133 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
136 HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) in getCompoundCandidateGroup()
142 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.cpp48 void markAsLaneMask(Register DstReg) const override;
58 Register DstReg, Register PrevReg,
408 Register DstReg = MI.getOperand(0).getReg(); in lowerCopiesFromI1() local
413 if (isLaneMaskReg(DstReg) || isVreg1(DstReg)) in lowerCopiesFromI1()
422 assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg)); in lowerCopiesFromI1()
426 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in lowerCopiesFromI1()
493 Register DstReg = MI->getOperand(0).getReg(); in lowerPhis() local
494 markAsLaneMask(DstReg); in lowerPhis()
495 initializeLaneMaskRegisterAttributes(DstReg); in lowerPhis()
509 PhiRegisters.insert(DstReg); in lowerPhis()
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H A DSIFixSGPRCopies.cpp206 Register DstReg = Copy.getOperand(0).getReg(); in getCopyRegClasses() local
216 const TargetRegisterClass *DstRC = DstReg.isVirtual() in getCopyRegClasses()
217 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
218 : TRI.getPhysRegBaseClass(DstReg); in getCopyRegClasses()
242 Register DstReg = MI.getOperand(0).getReg(); in tryChangeVGPRtoSGPRinCopy() local
244 if (!SrcReg.isVirtual() || !DstReg.isVirtual()) in tryChangeVGPRtoSGPRinCopy()
247 for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) { in tryChangeVGPRtoSGPRinCopy()
261 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
284 Register DstReg = MI.getOperand(0).getReg(); in foldVGPRCopyIntoRegSequence() local
285 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
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H A DR600ExpandSpecialInstrs.cpp127 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
128 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
131 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
197 Register DstReg = in runOnMachineFunction() local
227 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
231 Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
232 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
233 DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); in runOnMachineFunction()
253 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
H A DAMDGPUGlobalISelDivergenceLowering.cpp66 void markAsLaneMask(Register DstReg) const override;
76 Register DstReg, Register PrevReg,
90 void DivergenceLoweringHelper::markAsLaneMask(Register DstReg) const { in markAsLaneMask()
91 assert(MRI->getType(DstReg) == LLT::scalar(1)); in markAsLaneMask()
93 if (MRI->getRegClassOrNull(DstReg)) { in markAsLaneMask()
94 if (MRI->constrainRegClass(DstReg, ST->getBoolRC())) in markAsLaneMask()
99 MRI->setRegClass(DstReg, ST->getBoolRC()); in markAsLaneMask()
166 Register DstReg, Register PrevReg, Register CurReg) { in buildMergeLaneMasks() argument
178 B.buildInstr(OrOp, {DstReg}, {PrevMaskedReg, CurMaskedReg}); in buildMergeLaneMasks()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp124 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
127 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
131 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
144 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
146 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
161 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
163 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
172 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
175 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
179 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
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H A DHexagonGenMemAbsolute.cpp94 unsigned DstReg = MO.getReg(); in runOnMachineFunction() local
95 if (MRI->use_nodbg_empty(DstReg)) in runOnMachineFunction()
99 use_iterator NextUseMI = MRI->use_nodbg_begin(DstReg); in runOnMachineFunction()
134 if ((DstReg != BaseReg) || (Offset != 0)) in runOnMachineFunction()
177 .addReg(DstReg, RegState::Define); in runOnMachineFunction()
181 TII->get(NewOpc), DstReg); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp113 const Register DstReg,
128 bool emitInsertSubreg(Register DstReg, Register SrcReg, MachineInstr &I,
131 bool emitExtractSubreg(Register DstReg, Register SrcReg, MachineInstr &I,
283 Register DstReg = I.getOperand(0).getReg(); in selectCopy() local
284 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
285 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
291 if (DstReg.isPhysical()) { in selectCopy()
299 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy()
328 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
346 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); in selectCopy()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp42 const DebugLoc &DL, Register DstReg, in copyPhysReg() argument
46 if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
47 BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg) in copyPhysReg()
54 if (LoongArch::LSX128RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
55 BuildMI(MBB, MBBI, DL, get(LoongArch::VORI_B), DstReg) in copyPhysReg()
62 if (LoongArch::LASX256RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
63 BuildMI(MBB, MBBI, DL, get(LoongArch::XVORI_B), DstReg) in copyPhysReg()
70 if (LoongArch::CFRRegClass.contains(DstReg) && in copyPhysReg()
72 BuildMI(MBB, MBBI, DL, get(LoongArch::MOVGR2CF), DstReg) in copyPhysReg()
77 if (LoongArch::GPRRegClass.contains(DstReg) && in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp64 MachineInstr &MI, Register &SrcReg, Register &DstReg,
66 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
194 Register &DstReg, const GlobalValue *GVal, bool IsAma) { in processCandidate() argument
195 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
203 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processCandidate()
213 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma); in processCandidate()
218 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg) in processCandidate()
224 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); in processCandidate()
228 Register &DstReg, Register &SrcReg, const GlobalValue *GVal, in processDstReg() argument
230 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processDstReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp428 Register DstReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADDOp() local
431 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
433 MIB.addReg(DstReg); in selectSHXADDOp()
440 Register DstReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADDOp() local
443 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
445 MIB.addReg(DstReg); in selectSHXADDOp()
479 Register DstReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADDOp() local
482 .buildInstr(RISCV::SRLIW, {DstReg}, {RegY}) in selectSHXADDOp()
484 MIB.addReg(DstReg); in selectSHXADDOp()
516 Register DstReg = MRI->createVirtualRegister(&RISCV::GPRRegClass); in selectSHXADD_UWOp() local
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp128 bool isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg,
138 bool &IsCopy, Register &DstReg,
179 void scanUses(Register DstReg);
363 Register &DstReg, bool &IsSrcPhys, in isCopyToReg() argument
366 DstReg = 0; in isCopyToReg()
368 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
371 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
378 IsDstPhys = DstReg.isPhysical(); in isCopyToReg()
460 Register SrcReg, DstReg; in isKilled() local
463 if (!isCopyToReg(*DefMI, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp129 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
134 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) { in expandMOVImm()
160 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
164 .addReg(DstReg, RegState::Define | in expandMOVImm()
167 .addReg(DstReg) in expandMOVImm()
173 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
177 .addReg(DstReg, RegState::Define | in expandMOVImm()
180 .addReg(DstReg) in expandMOVImm()
181 .addReg(DstReg) in expandMOVImm()
192 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
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H A DAArch64RedundantCopyElimination.cpp181 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
190 SrcReg != DstReg) { in knownRegValInBlock()
204 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock()
209 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock()
213 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
247 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
248 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock()
253 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock()
258 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVPostRAExpandPseudoInsts.cpp90 Register DstReg = MBBI->getOperand(0).getReg(); in expandMovImm() local
94 TII->movImm(MBB, MBBI, DL, DstReg, Val, MachineInstr::NoFlags, Renamable, in expandMovImm()
105 Register DstReg = MBBI->getOperand(0).getReg(); in expandMovAddr() local
110 .addReg(DstReg, RegState::Define | getRenamableRegState(Renamable)) in expandMovAddr()
113 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead) | in expandMovAddr()
115 .addReg(DstReg, RegState::Kill | getRenamableRegState(Renamable)) in expandMovAddr()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp133 Register DstReg = I.getOperand(0).getReg(); in selectCopy() local
135 if (DstReg.isPhysical()) in selectCopy()
138 const RegisterBank *DstRegBank = RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
140 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
145 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
191 const Register DstReg = I.getOperand(0).getReg(); in selectIntToFP() local
199 bool IsSingle = MRI.getType(DstReg).getSizeInBits() == 32; in selectIntToFP()
205 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); in selectIntToFP()
218 const Register DstReg = I.getOperand(0).getReg(); in selectFPToInt() local
235 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg); in selectFPToInt()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp708 const DebugLoc &DL, Register DstReg, in copyPhysReg() argument
714 if (M68k::XR32RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
716 else if (M68k::XR16RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
718 else if (M68k::DR8RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
722 BuildMI(MBB, MI, DL, get(Opc), DstReg) in copyPhysReg()
735 if (M68k::XR16RegClass.contains(DstReg)) in copyPhysReg()
737 else if (M68k::XR32RegClass.contains(DstReg)) in copyPhysReg()
740 M68k::XR32RegClass.contains(DstReg)) in copyPhysReg()
744 BuildMI(MBB, MI, DL, get(Opc), DstReg) in copyPhysReg()
751 bool ToCCR = DstReg == M68k::CCR; in copyPhysReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp228 bool loadImmediate(int64_t ImmValue, MCRegister DstReg, MCRegister SrcReg,
232 bool loadAndAddSymbolAddress(const MCExpr *SymExpr, MCRegister DstReg,
250 bool expandLoadAddress(MCRegister DstReg, MCRegister BaseReg,
2138 MCOperand &DstReg = Inst.getOperand(0); in processInstruction() local
2142 Mips::GPRMM16RegClassID).contains(DstReg.getReg()) && in processInstruction()
2146 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset, in processInstruction()
2715 bool MipsAsmParser::loadImmediate(int64_t ImmValue, MCRegister DstReg, in loadImmediate() argument
2745 MCRegister TmpReg = DstReg; in loadImmediate()
2747 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { in loadImmediate()
2764 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp248 Register DstReg = MI.getOperand(0).getReg(); in selectMachineFunction() local
249 if (SrcReg.isVirtual() && DstReg.isVirtual()) { in selectMachineFunction()
251 auto DstRC = MRI.getRegClass(DstReg); in selectMachineFunction()
253 MRI.replaceRegWith(DstReg, SrcReg); in selectMachineFunction()
365 auto [DstReg, SrcReg] = MI.getFirst2Regs(); in selectInstr()
371 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in selectInstr()
374 assert(canReplaceReg(DstReg, SrcReg, MRI) && in selectInstr()
377 MRI.replaceRegWith(DstReg, SrcReg); in selectInstr()

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