Lines Matching refs:DstReg
129 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
134 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) { in expandMOVImm()
160 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
164 .addReg(DstReg, RegState::Define | in expandMOVImm()
167 .addReg(DstReg) in expandMOVImm()
173 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
177 .addReg(DstReg, RegState::Define | in expandMOVImm()
180 .addReg(DstReg) in expandMOVImm()
181 .addReg(DstReg) in expandMOVImm()
192 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
196 .addReg(DstReg, RegState::Define | in expandMOVImm()
199 .addReg(DstReg) in expandMOVImm()
209 .addReg(DstReg, RegState::Define | in expandMOVImm()
217 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
220 .addReg(DstReg, in expandMOVImm()
224 .addReg(DstReg) in expandMOVImm()
497 Register DstReg = MI.getOperand(0).getReg(); in expand_DestructiveOp() local
505 if (DstReg == MI.getOperand(3).getReg()) { in expand_DestructiveOp()
521 if (DstReg == MI.getOperand(3).getReg()) { in expand_DestructiveOp()
525 } else if (DstReg == MI.getOperand(4).getReg()) { in expand_DestructiveOp()
541 DOPRegIsUnique = DstReg != MI.getOperand(SrcIdx).getReg(); in expand_DestructiveOp()
546 DstReg != MI.getOperand(DOPIdx).getReg() || in expand_DestructiveOp()
555 DstReg != MI.getOperand(DOPIdx).getReg() || in expand_DestructiveOp()
617 .addReg(DstReg, RegState::Define) in expand_DestructiveOp()
632 .addReg(DstReg, RegState::Define) in expand_DestructiveOp()
634 .addReg(DstReg) in expand_DestructiveOp()
637 } else if (DstReg != MI.getOperand(DOPIdx).getReg()) { in expand_DestructiveOp()
640 .addReg(DstReg, RegState::Define) in expand_DestructiveOp()
649 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)); in expand_DestructiveOp()
1171 Register DstReg = MI.getOperand(0).getReg(); in expandMI() local
1172 if (DstReg == MI.getOperand(3).getReg()) { in expandMI()
1181 } else if (DstReg == MI.getOperand(2).getReg()) { in expandMI()
1192 if (DstReg == MI.getOperand(1).getReg()) { in expandMI()
1204 .addReg(DstReg, in expandMI()
1213 .addReg(DstReg, in expandMI()
1297 Register DstReg = MI.getOperand(0).getReg(); in expandMI() local
1304 TII->get(AArch64::LDRXl), DstReg); in expandMI()
1320 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg); in expandMI()
1325 unsigned Reg32 = TRI->getSubReg(DstReg, AArch64::sub_32); in expandMI()
1329 .addReg(DstReg, RegState::Kill) in expandMI()
1330 .addReg(DstReg, DstFlags | RegState::Implicit); in expandMI()
1332 Register DstReg = MI.getOperand(0).getReg(); in expandMI() local
1335 .addUse(DstReg, RegState::Kill); in expandMI()
1374 Register DstReg = MI.getOperand(0).getReg(); in expandMI() local
1376 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg) in expandMI()
1379 TII->get(AArch64::LDRXui), DstReg) in expandMI()
1380 .addUse(DstReg) in expandMI()
1395 Register DstReg = MI.getOperand(0).getReg(); in expandMI() local
1396 assert(DstReg != AArch64::XZR); in expandMI()
1398 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg) in expandMI()
1412 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi), DstReg) in expandMI()
1413 .addReg(DstReg) in expandMI()
1421 .addReg(DstReg) in expandMI()
1440 Register DstReg = MI.getOperand(0).getReg(); in expandMI() local
1451 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg) in expandMI()