69   void markAsLaneMask(Register DstReg) const override;
79                            Register DstReg, Register PrevReg,
477       Register DstReg = MI.getOperand(0).getReg();  in lowerCopiesFromI1()  local
482       if (isLaneMaskReg(DstReg) || isVreg1(DstReg))  in lowerCopiesFromI1()
491       assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg));  in lowerCopiesFromI1()
495       BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)  in lowerCopiesFromI1()
562     Register DstReg = MI->getOperand(0).getReg();  in lowerPhis()  local
563     markAsLaneMask(DstReg);  in lowerPhis()
564     initializeLaneMaskRegisterAttributes(DstReg);  in lowerPhis()
578     PhiRegisters.insert(DstReg);  in lowerPhis()
584     for (MachineInstr &Use : MRI->use_instructions(DstReg))  in lowerPhis()
596     SSAUpdater.Initialize(DstReg);  in lowerPhis()
645     if (NewReg != DstReg) {  in lowerPhis()
646       replaceDstReg(NewReg, DstReg, &MBB);  in lowerPhis()
669       Register DstReg = MI.getOperand(0).getReg();  in lowerCopiesToI1()  local
670       if (!isVreg1(DstReg))  in lowerCopiesToI1()
675       if (MRI->use_empty(DstReg)) {  in lowerCopiesToI1()
682       markAsLaneMask(DstReg);  in lowerCopiesToI1()
683       initializeLaneMaskRegisterAttributes(DstReg);  in lowerCopiesToI1()
708       for (MachineInstr &Use : MRI->use_instructions(DstReg))  in lowerCopiesToI1()
715         SSAUpdater.Initialize(DstReg);  in lowerCopiesToI1()
716         SSAUpdater.AddAvailableValue(&MBB, DstReg);  in lowerCopiesToI1()
719         buildMergeLaneMasks(MBB, MI, DL, DstReg,  in lowerCopiesToI1()
812 void Vreg1LoweringHelper::markAsLaneMask(Register DstReg) const {  in markAsLaneMask()
813   MRI->setRegClass(DstReg, ST->getBoolRC());  in markAsLaneMask()
856                                               Register DstReg, Register PrevReg,  in buildMergeLaneMasks()  argument
865       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);  in buildMergeLaneMasks()
867       BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);  in buildMergeLaneMasks()
869       BuildMI(MBB, I, DL, TII->get(XorOp), DstReg)  in buildMergeLaneMasks()
901     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
904     BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)  in buildMergeLaneMasks()
907     BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg)  in buildMergeLaneMasks()
911     BuildMI(MBB, I, DL, TII->get(OrOp), DstReg)  in buildMergeLaneMasks()