Lines Matching refs:DstReg
228 bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
232 bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
250 bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
2181 MCOperand &DstReg = Inst.getOperand(0); in processInstruction() local
2185 Mips::GPRMM16RegClassID).contains(DstReg.getReg()) && in processInstruction()
2189 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset, in processInstruction()
2759 bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, in loadImmediate() argument
2789 unsigned TmpReg = DstReg; in loadImmediate()
2791 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { in loadImmediate()
2808 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2812 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2817 unsigned TmpReg = DstReg; in loadImmediate()
2818 if (SrcReg == DstReg) { in loadImmediate()
2826 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2842 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2853 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2861 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2884 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2921 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2940 bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg, in expandLoadAddress() argument
2959 return loadAndAddSymbolAddress(Offset.getExpr(), DstReg, BaseReg, in expandLoadAddress()
2967 return loadImmediate(Offset.getImm(), DstReg, BaseReg, Is32BitAddress, true, in expandLoadAddress()
2972 unsigned DstReg, unsigned SrcReg, in loadAndAddSymbolAddress() argument
3010 if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg && in loadAndAddSymbolAddress()
3017 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc, in loadAndAddSymbolAddress()
3019 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg, in loadAndAddSymbolAddress()
3021 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, DstReg, in loadAndAddSymbolAddress()
3026 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg, in loadAndAddSymbolAddress()
3032 unsigned TmpReg = DstReg; in loadAndAddSymbolAddress()
3034 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, in loadAndAddSymbolAddress()
3076 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3141 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3168 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg); in loadAndAddSymbolAddress()
3191 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3194 } else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) { in loadAndAddSymbolAddress()
3208 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3211 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3215 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
3216 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI); in loadAndAddSymbolAddress()
3218 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3222 (canUseATReg() && DstReg == getATReg(IDLoc))) { in loadAndAddSymbolAddress()
3231 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3233 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3235 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3236 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3238 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3239 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg, in loadAndAddSymbolAddress()
3242 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3248 assert(SrcReg == DstReg && !canUseATReg() && in loadAndAddSymbolAddress()
3265 unsigned TmpReg = DstReg; in loadAndAddSymbolAddress()
3267 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { in loadAndAddSymbolAddress()
3281 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3284 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg)); in loadAndAddSymbolAddress()
3761 unsigned DstReg = DstRegOp.getReg(); in expandMem16Inst() local
3763 unsigned TmpReg = DstReg; in expandMem16Inst()
3772 if (!IsLoad || !IsGPR || (BaseReg == DstReg)) { in expandMem16Inst()
3782 TOut.emitRRX(OpCode, DstReg, TmpReg, Off, IDLoc, STI); in expandMem16Inst()
3784 TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, Off, IDLoc, STI); in expandMem16Inst()
3888 unsigned DstReg = DstRegOp.getReg(); in expandMem9Inst() local
3890 unsigned TmpReg = DstReg; in expandMem9Inst()
3899 if (!IsLoad || !IsGPR || (BaseReg == DstReg)) { in expandMem9Inst()
3909 TOut.emitRRX(OpCode, DstReg, TmpReg, MCOperand::createImm(0), IDLoc, STI); in expandMem9Inst()
3911 TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, MCOperand::createImm(0), in expandMem9Inst()
4456 unsigned DstReg = DstRegOp.getReg(); in expandUlh() local
4479 unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg; in expandUlh()
4480 unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg; in expandUlh()
4483 unsigned SllReg = IsLargeOffset ? DstReg : ATReg; in expandUlh()
4489 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUlh()
4508 unsigned DstReg = DstRegOp.getReg(); in expandUsh() local
4530 TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI); in expandUsh()
4531 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4532 TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI); in expandUsh()
4534 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4535 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUsh()
4537 TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI); in expandUsh()
4538 TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI); in expandUsh()
4559 unsigned DstReg = DstRegOp.getReg(); in expandUxw() local
4571 bool DoMove = IsLoadInst && (SrcReg == DstReg) && !IsLargeOffset; in expandUxw()
4587 std::swap(DstReg, TmpReg); in expandUxw()
4591 TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI); in expandUxw()
4592 TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI); in expandUxw()
4595 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI); in expandUxw()
4609 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSge() local
4628 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSge()
4629 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSge()
4643 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSgeImm() local
4668 TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI); in expandSgeImm()
4669 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4671 unsigned ImmReg = DstReg; in expandSgeImm()
4672 if (DstReg == SrcReg) { in expandSgeImm()
4683 TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI); in expandSgeImm()
4684 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4699 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSgtImm() local
4701 unsigned ImmReg = DstReg; in expandSgtImm()
4720 if (DstReg == SrcReg) { in expandSgtImm()
4732 TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI); in expandSgtImm()
4746 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSle() local
4765 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI); in expandSle()
4766 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSle()
4780 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSleImm() local
4801 unsigned ImmReg = DstReg; in expandSleImm()
4802 if (DstReg == SrcReg) { in expandSleImm()
4813 TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI); in expandSleImm()
4814 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSleImm()
4831 unsigned DstReg = Inst.getOperand(0).getReg(); in expandAliasImmediate() local
4839 if (DstReg == SrcReg) { in expandAliasImmediate()
4843 FinalDstReg = DstReg; in expandAliasImmediate()
4844 DstReg = ATReg; in expandAliasImmediate()
4847 if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false, in expandAliasImmediate()
4918 TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI); in expandAliasImmediate()
4920 TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI); in expandAliasImmediate()
5228 unsigned DstReg = Inst.getOperand(0).getReg(); in expandMulImm() local
5242 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulImm()
5251 unsigned DstReg = Inst.getOperand(0).getReg(); in expandMulO() local
5262 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5265 DstReg, DstReg, 0x1F, IDLoc, STI); in expandMulO()
5270 TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI); in expandMulO()
5277 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI); in expandMulO()
5284 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5293 unsigned DstReg = Inst.getOperand(0).getReg(); in expandMulOU() local
5305 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulOU()
5328 unsigned DstReg = Inst.getOperand(0).getReg(); in expandDMULMacro() local
5333 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandDMULMacro()
5437 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSeq() local
5444 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5445 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeq()
5450 TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI); in expandSeq()
5463 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSeqI() local
5470 TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI); in expandSeqI()
5477 DstReg, SrcReg, SrcReg, IDLoc, STI); in expandSeqI()
5498 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSeqI()
5499 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5503 TOut.emitRRI(Opc, DstReg, SrcReg, Imm, IDLoc, STI); in expandSeqI()
5504 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5518 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSne() local
5525 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSne()
5526 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSne()
5531 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI); in expandSne()
5544 unsigned DstReg = Inst.getOperand(0).getReg(); in expandSneI() local
5551 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI); in expandSneI()
5557 if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out, in expandSneI()
5572 TOut.emitRRI(Opc, DstReg, SrcReg, ImmValue, IDLoc, STI); in expandSneI()
5573 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()
5585 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSneI()
5586 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()