| /freebsd/sys/dev/sym/ |
| H A D | sym_defs.h | 303 #define CSEL 0x10 /* r/w: SCSI-SEL */ macro
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 2561 case AArch64ISD::CSEL: { in computeKnownBitsForTargetNode()
4104 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal, in LowerXOR()
4154 return DAG.getNode(AArch64ISD::CSEL, DL, Sel.getValueType(), FVal, TVal, in LowerXOR()
4184 return DAG.getNode(AArch64ISD::CSEL, DL, VT, One, Zero, CC, Glue); in carryFlagToValue()
4194 return DAG.getNode(AArch64ISD::CSEL, DL, VT, One, Zero, CC, Glue); in overflowFlagToValue()
4245 DAG.getNode(AArch64ISD::CSEL, DL, MVT::i32, FVal, TVal, CCVal, Overflow); in LowerXALUO()
7031 return DAG.getNode(AArch64ISD::CSEL, DL, VT, Op.getOperand(0), Neg, in LowerABS()
11041 SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, VT, FVal, TVal, CCVal, Cmp); in LowerSETCC()
11068 Res = DAG.getNode(AArch64ISD::CSEL, DL, VT, FVal, TVal, CC1Val, Cmp); in LowerSETCC()
11078 DAG.getNode(AArch64ISD::CSEL, DL, VT, TVal, FVal, CC1Val, Cmp); in LowerSETCC()
[all …]
|
| H A D | AArch64SchedThunderX2T99.td | 434 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
456 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
475 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
|
| H A D | AArch64SchedThunderX3T110.td | 694 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
716 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
735 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
|
| H A D | AArch64SchedA64FX.td | 610 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
630 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
647 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
|
| H A D | AArch64SchedCyclone.td | 149 // CSEL,CSINC,CSINV,CSNEG
|
| H A D | AArch64SchedTSV110.td | 404 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
|
| H A D | AArch64SchedAmpere1.td | 952 (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>;
|
| H A D | AArch64SchedAmpere1B.td | 934 (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>;
|
| H A D | AArch64SchedFalkorDetails.td | 894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
|
| H A D | AArch64SchedOryon.td | 700 (instregex "^CSEL(W|X)r", "^CSINV(W|X)r",
|
| H A D | AArch64SchedKryoDetails.td | 543 (instregex "CSEL(W|X)r")>;
|
| H A D | AArch64InstrInfo.td | 822 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
3355 defm CSEL : CondSelect<0, 0b00, "csel">;
5589 // CSEL instructions providing f128 types need to be handled by a
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleM85.td | 556 (instregex "t2(CSEL|CSINC|CSINV|CSNEG)")>;
|
| H A D | ARMInstrThumb2.td | 426 // CSEL aliases inverted predicate
758 // CSEL). Setting Unpredictable{15} = 1 here would reintroduce
|