2323   case AArch64ISD::CSEL: {  in computeKnownBitsForTargetNode()
2554     MAKE_CASE(AArch64ISD::CSEL)  in getTargetNodeName()
4091     return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,  in LowerXOR()
4141     return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,  in LowerXOR()
4171   return DAG.getNode(AArch64ISD::CSEL, DL, VT, One, Zero, CC, Glue);  in carryFlagToValue()
4181   return DAG.getNode(AArch64ISD::CSEL, DL, VT, One, Zero, CC, Glue);  in overflowFlagToValue()
4231   Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,  in LowerXALUO()
6606   return DAG.getNode(AArch64ISD::CSEL, DL, VT, Op.getOperand(0), Neg,  in LowerABS()
10352     SDValue Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);  in LowerSETCC()
10379     Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);  in LowerSETCC()
10389         DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);  in LowerSETCC()
10392     Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);  in LowerSETCC()
10423   return DAG.getNode(AArch64ISD::CSEL, DL, OpVT, FVal, TVal, CCVal,  in LowerSETCCCARRY()
10490     unsigned Opcode = AArch64ISD::CSEL;  in LowerSELECT_CC()
10568       if (Opcode != AArch64ISD::CSEL) {  in LowerSELECT_CC()
10581     if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&  in LowerSELECT_CC()
10640   SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);  in LowerSELECT_CC()
10646     return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);  in LowerSELECT_CC()
10748     return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,  in LowerSELECT()
18765   if (CSel0.getOpcode() != AArch64ISD::CSEL ||  in performANDORCSELCombine()
18766       CSel1.getOpcode() != AArch64ISD::CSEL)  in performANDORCSELCombine()
18823   return DAG.getNode(AArch64ISD::CSEL, DL, VT, CSel0.getOperand(0),  in performANDORCSELCombine()
19757   if (Op.getOpcode() != AArch64ISD::CSEL)  in isSetCC()
19843   return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);  in performSetccAddFolding()
19895   if (LHS.getOpcode() != AArch64ISD::CSEL &&  in performAddCSelIntoCSinc()
19898     if (LHS.getOpcode() != AArch64ISD::CSEL &&  in performAddCSelIntoCSinc()
19917   if (!(LHS.getOpcode() == AArch64ISD::CSEL &&  in performAddCSelIntoCSinc()
19924   if (LHS.getOpcode() == AArch64ISD::CSEL && CTVal->isOne() &&  in performAddCSelIntoCSinc()
19947   assert(((LHS.getOpcode() == AArch64ISD::CSEL && CFVal->isOne()) ||  in performAddCSelIntoCSinc()
20004   if (CSel.getOpcode() != AArch64ISD::CSEL || !CSel->hasOneUse())  in performNegCSelCombine()
20020   return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0N, N1N, CSel.getOperand(2),  in performNegCSelCombine()
20085   if (Op.getOpcode() != AArch64ISD::CSEL)  in getCSETCondCode()
21091   SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test);  in getPTest()
23753   if (CmpRHS.getOpcode() == AArch64ISD::CSEL)  in foldCSELOfCSEL()
23755   else if (CmpLHS.getOpcode() != AArch64ISD::CSEL)  in foldCSELOfCSEL()
23790   return DAG.getNode(AArch64ISD::CSEL, DL, VT, L, R, CCValue, Cond);  in foldCSELOfCSEL()
23891       LHS->getOpcode() == AArch64ISD::CSEL &&  in performSETCCCombine()
23900     SDValue CSEL =  in performSETCCCombine()  local
23901         DAG.getNode(AArch64ISD::CSEL, DL, LHS.getValueType(), LHS.getOperand(0),  in performSETCCCombine()
23904     return DAG.getZExtOrTrunc(CSEL, DL, VT);  in performSETCCCombine()
25355   case AArch64ISD::CSEL:  in PerformDAGCombine()