| /freebsd/sys/riscv/vmm/ |
| H A D | vmm_vtimer.h | 9be0058ea0fc6fd098b9e2ab54f94c86fe7eb69a Thu Jan 02 16:42:34 CET 2025 Ruslan Bukin <br@FreeBSD.org> riscv vmm: virtual timer support.
Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.
Timer interrupt pending bit (STIP) could not be cleared in the guest system,
so rework interrupts handling: add new "interrupts_pending" field. Use it
for timer interrupt only for now, but later we can extend to store all
pending interrupts (Timer, IPI and External).
With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550,
which is the first real hardware with RISC-V 'H'-spec included.
Differential Revision: https://reviews.freebsd.org/D48133
|
| H A D | vmm_vtimer.c | 9be0058ea0fc6fd098b9e2ab54f94c86fe7eb69a Thu Jan 02 16:42:34 CET 2025 Ruslan Bukin <br@FreeBSD.org> riscv vmm: virtual timer support.
Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.
Timer interrupt pending bit (STIP) could not be cleared in the guest system,
so rework interrupts handling: add new "interrupts_pending" field. Use it
for timer interrupt only for now, but later we can extend to store all
pending interrupts (Timer, IPI and External).
With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550,
which is the first real hardware with RISC-V 'H'-spec included.
Differential Revision: https://reviews.freebsd.org/D48133
|
| H A D | riscv.h | diff 9be0058ea0fc6fd098b9e2ab54f94c86fe7eb69a Thu Jan 02 16:42:34 CET 2025 Ruslan Bukin <br@FreeBSD.org> riscv vmm: virtual timer support.
Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.
Timer interrupt pending bit (STIP) could not be cleared in the guest system,
so rework interrupts handling: add new "interrupts_pending" field. Use it
for timer interrupt only for now, but later we can extend to store all
pending interrupts (Timer, IPI and External).
With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550,
which is the first real hardware with RISC-V 'H'-spec included.
Differential Revision: https://reviews.freebsd.org/D48133
|
| H A D | vmm_sbi.c | diff 9be0058ea0fc6fd098b9e2ab54f94c86fe7eb69a Thu Jan 02 16:42:34 CET 2025 Ruslan Bukin <br@FreeBSD.org> riscv vmm: virtual timer support.
Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.
Timer interrupt pending bit (STIP) could not be cleared in the guest system,
so rework interrupts handling: add new "interrupts_pending" field. Use it
for timer interrupt only for now, but later we can extend to store all
pending interrupts (Timer, IPI and External).
With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550,
which is the first real hardware with RISC-V 'H'-spec included.
Differential Revision: https://reviews.freebsd.org/D48133
|
| H A D | vmm_riscv.c | diff 9be0058ea0fc6fd098b9e2ab54f94c86fe7eb69a Thu Jan 02 16:42:34 CET 2025 Ruslan Bukin <br@FreeBSD.org> riscv vmm: virtual timer support.
Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.
Timer interrupt pending bit (STIP) could not be cleared in the guest system,
so rework interrupts handling: add new "interrupts_pending" field. Use it
for timer interrupt only for now, but later we can extend to store all
pending interrupts (Timer, IPI and External).
With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550,
which is the first real hardware with RISC-V 'H'-spec included.
Differential Revision: https://reviews.freebsd.org/D48133
|
| H A D | vmm.c | diff 9be0058ea0fc6fd098b9e2ab54f94c86fe7eb69a Thu Jan 02 16:42:34 CET 2025 Ruslan Bukin <br@FreeBSD.org> riscv vmm: virtual timer support.
Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.
Timer interrupt pending bit (STIP) could not be cleared in the guest system,
so rework interrupts handling: add new "interrupts_pending" field. Use it
for timer interrupt only for now, but later we can extend to store all
pending interrupts (Timer, IPI and External).
With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550,
which is the first real hardware with RISC-V 'H'-spec included.
Differential Revision: https://reviews.freebsd.org/D48133
|
| /freebsd/usr.sbin/bhyve/riscv/ |
| H A D | fdt.c | diff 9be0058ea0fc6fd098b9e2ab54f94c86fe7eb69a Thu Jan 02 16:42:34 CET 2025 Ruslan Bukin <br@FreeBSD.org> riscv vmm: virtual timer support.
Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.
Timer interrupt pending bit (STIP) could not be cleared in the guest system,
so rework interrupts handling: add new "interrupts_pending" field. Use it
for timer interrupt only for now, but later we can extend to store all
pending interrupts (Timer, IPI and External).
With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550,
which is the first real hardware with RISC-V 'H'-spec included.
Differential Revision: https://reviews.freebsd.org/D48133
|
| /freebsd/sys/modules/vmm/ |
| H A D | Makefile | diff 9be0058ea0fc6fd098b9e2ab54f94c86fe7eb69a Thu Jan 02 16:42:34 CET 2025 Ruslan Bukin <br@FreeBSD.org> riscv vmm: virtual timer support.
Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.
Timer interrupt pending bit (STIP) could not be cleared in the guest system,
so rework interrupts handling: add new "interrupts_pending" field. Use it
for timer interrupt only for now, but later we can extend to store all
pending interrupts (Timer, IPI and External).
With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550,
which is the first real hardware with RISC-V 'H'-spec included.
Differential Revision: https://reviews.freebsd.org/D48133
|
| /freebsd/sys/conf/ |
| H A D | files.riscv | diff 9be0058ea0fc6fd098b9e2ab54f94c86fe7eb69a Thu Jan 02 16:42:34 CET 2025 Ruslan Bukin <br@FreeBSD.org> riscv vmm: virtual timer support.
Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.
Timer interrupt pending bit (STIP) could not be cleared in the guest system,
so rework interrupts handling: add new "interrupts_pending" field. Use it
for timer interrupt only for now, but later we can extend to store all
pending interrupts (Timer, IPI and External).
With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550,
which is the first real hardware with RISC-V 'H'-spec included.
Differential Revision: https://reviews.freebsd.org/D48133
|