riscv vmm: clean up SBI code

- Use SBI standard error codes (with respect to the spec)
- riscv_send_ipi() now takes cpuset_t* as an argument

Differential Revision: https://reviews.freebsd.org/D48575

riscv vmm: implement SBI RFNC extension.

The RISC-V SBI (Supervisor Binary Interface) RFNC (fence) extension is used
to provide a standardized mechanism for enforcing memory and I/O ordering
between

riscv vmm: implement SBI RFNC extension.

The RISC-V SBI (Supervisor Binary Interface) RFNC (fence) extension is used
to provide a standardized mechanism for enforcing memory and I/O ordering
between different execution contexts or cores in a system. Specifically, it
allows supervisors (such as an operating system kernel) to request certain
synchronization operations across CPUs or harts (hardware threads) via the
SBI.

Differential Revision: https://reviews.freebsd.org/D48441

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riscv vmm: virtual timer support.

Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.

Timer interru

riscv vmm: virtual timer support.

Add a virtual timer implementation based on SBI Time extension.
This is needed for Eswin EIC7700 SoC which does not include the newer SSTC
extension.

Timer interrupt pending bit (STIP) could not be cleared in the guest system,
so rework interrupts handling: add new "interrupts_pending" field. Use it
for timer interrupt only for now, but later we can extend to store all
pending interrupts (Timer, IPI and External).

With this I'm able to boot FreeBSD (SMP) guest on HiFive Premier P550,
which is the first real hardware with RISC-V 'H'-spec included.

Differential Revision: https://reviews.freebsd.org/D48133

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riscv/vmm: Initial import.

Add kernel code for 'H' — Hypervisor Extension[1] to support
virtualization on RISC-V ISA.

This comes with a separate userspace patch allowing us to boot
unmodified freeb

riscv/vmm: Initial import.

Add kernel code for 'H' — Hypervisor Extension[1] to support
virtualization on RISC-V ISA.

This comes with a separate userspace patch allowing us to boot
unmodified freebsd/riscv guest. Other operating systems are untested.

This also comes with a U-Boot port that is configured to run in bhyve
guest environment — in RISC-V virtual supervisor mode.
The vmm SBI code emulates RISC-V machine-mode for the guest, handling
SBI calls partly in vmm kernel and partly in bhyve userspace.

Developed in Spike simulator during short period of time, the support
is considered experimental. The first real hardware with hypervisor
spec included should have just reached the market, so this was tested
in Spike and QEMU only. Note that this depends on Sstc extension
presence in the hardware (both Spike and QEMU have it).

Note that booting multiple guests at the same time is not tested and
may require additional work. Some TODOs are indicated within the
code, and some listed in the project's home page[2].

Many thanks to Jessica Clarke, Mitchell Horne and Mark Johnston
for help with parts, test and review.

1. https://riscv.org/technical/specifications/
2. https://wiki.freebsd.org/riscv/bhyve

Sponsored by: UK Research and Innovation
Differential Revision: https://reviews.freebsd.org/D45553

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