Searched hist:"80 e4c1cd42fff110bfdae8fce7ac4f22465f9664" (Results 1 – 3 of 3) sorted by relevance
| /linux/arch/x86/include/asm/ |
| H A D | disabled-features.h | diff 80e4c1cd42fff110bfdae8fce7ac4f22465f9664 Thu Sep 15 13:11:19 CEST 2022 Thomas Gleixner <tglx@linutronix.de> x86/retbleed: Add X86_FEATURE_CALL_DEPTH
Intel SKL CPUs fall back to other predictors when the RSB underflows. The
only microcode mitigation is IBRS which is insanely expensive. It comes
with performance drops of up to 30% depending on the workload.
A way less expensive, but nevertheless horrible mitigation is to track the
call depth in software and overeagerly fill the RSB when returns underflow
the software counter.
Provide a configuration symbol and a CPU misfeature bit.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220915111147.056176424@infradead.org
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| H A D | cpufeatures.h | diff 80e4c1cd42fff110bfdae8fce7ac4f22465f9664 Thu Sep 15 13:11:19 CEST 2022 Thomas Gleixner <tglx@linutronix.de> x86/retbleed: Add X86_FEATURE_CALL_DEPTH
Intel SKL CPUs fall back to other predictors when the RSB underflows. The
only microcode mitigation is IBRS which is insanely expensive. It comes
with performance drops of up to 30% depending on the workload.
A way less expensive, but nevertheless horrible mitigation is to track the
call depth in software and overeagerly fill the RSB when returns underflow
the software counter.
Provide a configuration symbol and a CPU misfeature bit.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220915111147.056176424@infradead.org
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| /linux/arch/x86/ |
| H A D | Kconfig | diff 80e4c1cd42fff110bfdae8fce7ac4f22465f9664 Thu Sep 15 13:11:19 CEST 2022 Thomas Gleixner <tglx@linutronix.de> x86/retbleed: Add X86_FEATURE_CALL_DEPTH
Intel SKL CPUs fall back to other predictors when the RSB underflows. The
only microcode mitigation is IBRS which is insanely expensive. It comes
with performance drops of up to 30% depending on the workload.
A way less expensive, but nevertheless horrible mitigation is to track the
call depth in software and overeagerly fill the RSB when returns underflow
the software counter.
Provide a configuration symbol and a CPU misfeature bit.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220915111147.056176424@infradead.org
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