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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-div6-clock.yaml63 "zx", "zs", "hp", "ztr", "zt";
/linux/drivers/clk/renesas/
H A Dclk-r8a7740.c40 { "ztr", CPG_FRQCRB, 20 },
H A Dclk-r8a73a4.c45 { "ztr", CPG_FRQCRB, 20 },
H A Dr8a77995-cpg-mssr.c83 DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
H A Dr8a77980-cpg-mssr.c76 DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
H A Dr8a774c0-cpg-mssr.c88 DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1),
H A Dr8a779a0-cpg-mssr.c116 DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
H A Dr8a77990-cpg-mssr.c88 DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
H A Dr8a774b1-cpg-mssr.c77 DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
H A Dr8a774e1-cpg-mssr.c80 DEF_FIXED("ztr", R8A774E1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
H A Dr8a77965-cpg-mssr.c80 DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
H A Dr8a774a1-cpg-mssr.c80 DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
H A Dr8a7795-cpg-mssr.c83 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
H A Dr8a7796-cpg-mssr.c85 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),