Home
last modified time | relevance | path

Searched full:xtal (Results 1 – 25 of 290) sorted by relevance

12345678910>>...12

/linux/Documentation/devicetree/bindings/clock/
H A Darmada3700-xtal-clock.txt1 * Xtal Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
12 "marvell,armada-3700-xtal-clock"
17 output names ("xtal")
24 xtalclk: xtal-clk {
25 compatible = "marvell,armada-3700-xtal-clock";
26 clock-output-names = "xtal";
H A Dsilabs,si5351.yaml50 - const: xtal
62 - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only).
106 2 - use XTAL for this output
212 /* Connect XTAL input to 25MHz reference */
214 clock-names = "xtal";
216 /* Use XTAL input as source of PLL0 and PLL1 */
258 * - XTAL as clock source of output divider
H A Dmarvell,armada-3700-uart-clock.yaml23 "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"
28 used for UART (most probably xtal) for smooth boot log on UART.
36 - const: xtal
57 clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal";
H A Damlogic,s4-pll-clkc.yaml25 - const: xtal
44 clocks = <&xtal>;
45 clock-names = "xtal";
/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-t7-a311d2-an400.dts27 xtal: xtal-clk { label
30 clock-output-names = "xtal";
36 clocks = <&xtal>, <&xtal>, <&xtal>;
37 clock-names = "xtal", "pclk", "baud";
H A Dmeson-gxbb.dtsi286 clocks = <&xtal>, <&clkc CLKID_CLK81>;
287 clock-names = "xtal", "mpeg-clk";
322 assigned-clock-parents = <&xtal>, <0>;
330 clocks = <&xtal>;
331 clock-names = "xtal";
743 clocks = <&xtal>,
750 clocks = <&xtal>, <&clkc CLKID_CLK81>;
754 clocks = <&xtal>,
761 clocks = <&xtal>,
814 clocks = <&xtal>,
[all …]
H A Damlogic-t7-a311d2-khadas-vim4.dts41 xtal: xtal-clk { label
44 clock-output-names = "xtal";
52 clocks = <&xtal>, <&xtal>, <&xtal>;
53 clock-names = "xtal", "pclk", "baud";
H A Damlogic-a4-common.dtsi23 xtal: xtal-clk { label
26 clock-output-names = "xtal";
58 clocks = <&xtal>;
66 clocks = <&xtal>, <&xtal>, <&xtal>;
67 clock-names = "xtal", "pclk", "baud";
H A Dmeson-gxl.dtsi310 clocks = <&xtal>, <&clkc CLKID_CLK81>;
311 clock-names = "xtal", "mpeg-clk";
334 assigned-clock-parents = <&xtal>, <0>;
342 clocks = <&xtal>;
343 clock-names = "xtal";
813 clocks = <&xtal>,
820 clocks = <&xtal>, <&clkc CLKID_CLK81>;
824 clocks = <&xtal>,
831 clocks = <&xtal>,
884 clocks = <&xtal>,
[all …]
H A Dmeson-a1.dtsi489 <&xtal>;
492 "hifi_pll", "xtal";
511 clocks = <&xtal>, <&xtal>, <&xtal>;
512 clock-names = "xtal", "pclk", "baud";
521 clocks = <&xtal>, <&xtal>, <&xtal>;
522 clock-names = "xtal", "pclk", "baud";
555 clocks = <&xtal>,
600 clock-names = "xtal";
663 assigned-clock-parents = <&xtal>;
743 xtal: xtal-clk { label
[all …]
H A Damlogic-s7.dtsi59 xtal: xtal-clk { label
62 clock-output-names = "xtal";
94 clocks = <&xtal>, <&xtal>, <&xtal>;
95 clock-names = "xtal", "pclk", "baud";
H A Damlogic-s6.dtsi57 xtal: xtal-clk { label
60 clock-output-names = "xtal";
92 clocks = <&xtal>, <&xtal>, <&xtal>;
93 clock-names = "xtal", "pclk", "baud";
H A Damlogic-s7d.dtsi59 xtal: xtal-clk { label
62 clock-output-names = "xtal";
94 clocks = <&xtal>, <&xtal>, <&xtal>;
95 clock-names = "xtal", "pclk", "baud";
H A Dmeson-s4.dtsi62 xtal: xtal-clk { label
65 clock-output-names = "xtal";
121 <&xtal>;
125 "mpll2", "mpll3", "hdmi_pll", "xtal";
132 clocks = <&xtal>;
133 clock-names = "xtal";
140 clocks = <&xtal>;
606 <&xtal>,
760 clocks = <&xtal>, <&clkc_periphs CLKID_UART_B>, <&xtal>;
761 clock-names = "xtal", "pclk", "baud";
[all …]
H A Dmeson-g12-common.dtsi220 assigned-clock-parents = <&xtal>, <0>;
1571 clocks = <&xtal>;
1572 clock-names = "xtal";
1599 clocks = <&xtal>;
1600 clock-names = "xtal";
1621 clocks = <&xtal>;
1622 clock-names = "xtal";
1709 <&xtal>,
1754 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1755 clock-names = "xtal", "mpeg-clk";
[all …]
H A Dmeson-axg.dtsi1251 clocks = <&xtal>;
1252 clock-names = "xtal";
1575 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1576 clock-names = "xtal", "mpeg-clk";
1698 clocks = <&xtal>,
1710 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1711 clock-names = "xtal", "pclk", "baud";
1719 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1720 clock-names = "xtal", "pclk", "baud";
1737 clocks = <&xtal>,
[all …]
/linux/drivers/clk/pistachio/
H A Dclk-pistachio.c70 DIV(CLK_RPU_SLEEP_DIV, "rpu_sleep_div", "xtal", 0x224, 10),
105 PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
106 PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
107 PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
109 PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
110 PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
112 PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
113 PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
114 PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
117 PNAME(mux_xtal_sys) = { "xtal", "sys_pll" };
[all …]
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8.dtsi256 clocks = <&xtal>;
257 clock-names = "xtal";
453 clocks = <&xtal>,
601 xtal_32k_out_pins: xtal-32k-out {
604 function = "xtal";
650 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
651 clock-names = "xtal", "ddr_pll";
725 clocks = <&xtal>,
733 clocks = <&xtal>,
746 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
[all …]
H A Dmeson8b.dtsi233 clocks = <&xtal>;
234 clock-names = "xtal";
408 clocks = <&xtal>,
593 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
594 clock-names = "xtal", "ddr_pll";
682 clocks = <&xtal>,
690 clocks = <&xtal>,
703 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
712 clocks = <&xtal>,
734 clocks = <&xtal>, <&clkc CLKID_CLK81>;
[all …]
/linux/Documentation/devicetree/bindings/serial/
H A Damlogic,meson-uart.yaml73 - description: external xtal clock identifier
75 - description: the source of the baudrate generator, can be either the xtal or the pclk
79 - const: xtal
103 clocks = <&xtal>, <&pclk>, <&xtal>;
104 clock-names = "xtal", "pclk", "baud";
/linux/drivers/media/pci/cx18/
H A Dcx18-av-audio.c66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
101 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
105 /* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/ in set_audclk_freq()
109 /* 0x1.6d59 = (4 * xtal/8*2/455) / 44100 */ in set_audclk_freq()
136 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
140 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/ in set_audclk_freq()
144 /* 0x1.4faa = (4 * xtal/8*2/455) / 48000 */ in set_audclk_freq()
173 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
[all …]
/linux/Documentation/devicetree/bindings/soc/amlogic/
H A Damlogic,meson-gx-hhi-sysctrl.yaml125 clocks = <&xtal>;
126 clock-names = "xtal";
170 clocks = <&xtal>, <&clk81>;
171 clock-names = "xtal", "mpeg-clk";
184 clocks = <&xtal>;
185 clock-names = "xtal";
/linux/drivers/clk/renesas/
H A Drcar-usb2-clock-sel.c40 bool xtal; member
49 priv->extal, priv->xtal, val); in usb2_clock_sel_enable_extal_only()
51 if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY) in usb2_clock_sel_enable_extal_only()
57 if (priv->extal && !priv->xtal) in usb2_clock_sel_disable_extal_only()
169 priv->xtal = !!clk_get_rate(clk); in rcar_usb2_clock_sel_probe()
173 if (!priv->extal && !priv->xtal) { in rcar_usb2_clock_sel_probe()
/linux/drivers/clk/mvebu/
H A Darmada-37xx-xtal.c3 * Marvell Armada 37xx SoC xtal clocks
22 const char *xtal_name = "xtal"; in armada_3700_xtal_clock_probe()
74 { .compatible = "marvell,armada-3700-xtal-clock", },
82 .name = "marvell-armada-3700-xtal-clock",
/linux/drivers/phy/ralink/
H A Dphy-mt7621-pci.c70 * @sys_clk: pointer to the system XTAL clock
127 /* Debug Xtal Type */ in mt7621_set_phy_for_ssc()
142 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
147 dev_dbg(dev, "Xtal is 40MHz\n"); in mt7621_set_phy_for_ssc()
174 dev_dbg(dev, "Xtal is 25MHz\n"); in mt7621_set_phy_for_ssc()
175 } else { /* 20MHz Xtal */ in mt7621_set_phy_for_ssc()
179 dev_dbg(dev, "Xtal is 20MHz\n"); in mt7621_set_phy_for_ssc()
199 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()

12345678910>>...12