/linux/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mt8188.c | 27 PIN_FIELD(0, 177, 0x0300, 0x10, 0, 4), 31 PIN_FIELD(0, 177, 0x0000, 0x10, 0, 1), 35 PIN_FIELD(0, 177, 0x0200, 0x10, 0, 1), 39 PIN_FIELD(0, 177, 0x0100, 0x10, 0, 1), 43 PIN_FIELD_BASE(0, 0, 1, 0x0170, 0x10, 8, 1), 44 PIN_FIELD_BASE(1, 1, 1, 0x0170, 0x10, 9, 1), 45 PIN_FIELD_BASE(2, 2, 1, 0x0170, 0x10, 10, 1), 46 PIN_FIELD_BASE(3, 3, 1, 0x0170, 0x10, 11, 1), 47 PIN_FIELD_BASE(4, 4, 1, 0x0170, 0x10, 18, 1), 48 PIN_FIELD_BASE(5, 5, 1, 0x0170, 0x10, 18, 1), [all …]
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H A D | pinctrl-mt8192.c | 29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4), 33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1), 37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1), 41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1), 45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1), 46 PIN_FIELD_BASE(1, 1, 4, 0x00f0, 0x10, 8, 1), 47 PIN_FIELD_BASE(2, 2, 4, 0x00f0, 0x10, 8, 1), 48 PIN_FIELD_BASE(3, 3, 4, 0x00f0, 0x10, 8, 1), 49 PIN_FIELD_BASE(4, 4, 4, 0x00f0, 0x10, 8, 1), 50 PIN_FIELD_BASE(5, 5, 4, 0x00f0, 0x10, 9, 1), [all …]
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H A D | pinctrl-mt8186.c | 26 PIN_FIELD(0, 184, 0x300, 0x10, 0, 4), 30 PIN_FIELD(0, 184, 0x0, 0x10, 0, 1), 34 PIN_FIELD(0, 184, 0x200, 0x10, 0, 1), 38 PIN_FIELD(0, 184, 0x100, 0x10, 0, 1), 42 PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1), 43 PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1), 44 PIN_FIELD_BASE(2, 2, 6, 0x0030, 0x10, 17, 1), 45 PIN_FIELD_BASE(3, 3, 6, 0x0030, 0x10, 18, 1), 46 PIN_FIELD_BASE(4, 4, 6, 0x0030, 0x10, 19, 1), 47 PIN_FIELD_BASE(5, 5, 6, 0x0030, 0x10, 20, 1), [all …]
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H A D | pinctrl-mt8195.c | 28 PIN_FIELD(0, 144, 0x300, 0x10, 0, 4), 32 PIN_FIELD(0, 144, 0x0, 0x10, 0, 1), 36 PIN_FIELD(0, 144, 0x200, 0x10, 0, 1), 40 PIN_FIELD(0, 144, 0x100, 0x10, 0, 1), 44 PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1), 45 PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1), 46 PIN_FIELD_BASE(2, 2, 4, 0x040, 0x10, 2, 1), 47 PIN_FIELD_BASE(3, 3, 4, 0x040, 0x10, 3, 1), 48 PIN_FIELD_BASE(4, 4, 4, 0x040, 0x10, 4, 1), 49 PIN_FIELD_BASE(5, 5, 4, 0x040, 0x10, 5, 1), [all …]
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H A D | pinctrl-mt8183.c | 28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4), 32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1), 36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1), 40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1), 44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1), 45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1), 46 PIN_FIELD_BASE(8, 8, 6, 0x000, 0x10, 0, 1), 47 PINS_FIELD_BASE(9, 10, 6, 0x000, 0x10, 12, 1), 48 PIN_FIELD_BASE(11, 11, 1, 0x000, 0x10, 3, 1), 49 PIN_FIELD_BASE(12, 12, 1, 0x000, 0x10, 7, 1), [all …]
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H A D | pinctrl-mt6795.c | 23 PIN_FIELD16(0, 196, 0x0, 0x10, 0, 1), 27 PIN_FIELD16(0, 196, 0x100, 0x10, 0, 1), 31 PIN_FIELD16(0, 196, 0x200, 0x10, 0, 1), 35 PIN_FIELD16(0, 196, 0x400, 0x10, 0, 1), 39 PIN_FIELD16(0, 196, 0x500, 0x10, 0, 1), 43 PIN_FIELD15(0, 196, 0x600, 0x10, 0, 3), 47 PINS_FIELD16(0, 4, 0x900, 0x10, 1, 1), 48 PINS_FIELD16(5, 9, 0x900, 0x10, 2, 1), 49 PINS_FIELD16(10, 15, 0x900, 0x10, 10, 1), 50 PINS_FIELD16(16, 16, 0x900, 0x10, 2, 1), [all …]
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H A D | pinctrl-mt7986.c | 76 PIN_FIELD(0, 100, 0x300, 0x10, 0, 4), 80 PIN_FIELD(0, 100, 0x0, 0x10, 0, 1), 84 PIN_FIELD(0, 100, 0x200, 0x10, 0, 1), 88 PIN_FIELD(0, 100, 0x100, 0x10, 0, 1), 92 PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1), 93 PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1), 94 PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1), 95 PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1), 96 PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1), 97 PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1), [all …]
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H A D | pinctrl-mt7981.c | 23 PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), 27 PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), 31 PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), 35 PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), 39 PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), 40 PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), 41 PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), 42 PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), 43 PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), 44 PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), [all …]
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H A D | pinctrl-mt7623.c | 36 PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3), 40 PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1), 41 PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1), 45 PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1), 49 PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1), 53 PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1), 54 PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1), 55 PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1), 56 PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1), 57 PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1), [all …]
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/linux/fs/unicode/ |
H A D | utf8data.c_shipped | 96 0xe1,0x8d,0xa9,0x10,0x08,0x01,0xff,0xe8,0xb1,0x88,0x00,0x01,0xff,0xe6,0x9b,0xb4, 98 0xab,0x10,0x08,0x01,0xff,0xe9,0xb9,0xbf,0x00,0x01,0xff,0xe8,0xab,0x96,0x00,0xe3, 99 0x09,0xac,0xe2,0xe8,0xab,0xe1,0xd7,0xab,0x10,0x08,0x01,0xff,0xe7,0xb8,0xb7,0x00, 109 0x4e,0xe3,0xe2,0x2d,0xe3,0xe1,0x1b,0xe3,0x10,0x08,0x05,0xff,0xe4,0xb8,0xbd,0x00, 111 0xe2,0x0e,0xe5,0xe1,0xfd,0xe4,0x10,0x08,0x05,0xff,0xe5,0x92,0xa2,0x00,0x05,0xff, 112 0xe5,0x93,0xb6,0x00,0xd4,0x34,0xd3,0x18,0xe2,0xf7,0xe5,0xe1,0xe6,0xe5,0x10,0x09, 114 0xe6,0x91,0x11,0x10,0x09,0x05,0xff,0xf0,0xa1,0x8d,0xaa,0x00,0x05,0xff,0xe5,0xac, 116 0x10,0x08,0x05,0xff,0xe5,0xaf,0xb3,0x00,0x05,0xff,0xf0,0xa1,0xac,0x98,0x00,0xe1, 117 0x38,0xe6,0x10,0x08,0x05,0xff,0xe5,0xbc,0xb3,0x00,0x05,0xff,0xe5,0xb0,0xa2,0x00, 119 0xea,0xe1,0x93,0xea,0x10,0x08,0x05,0xff,0xe6,0xb4,0xbe,0x00,0x05,0xff,0xe6,0xb5, [all …]
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/linux/include/linux/mlx5/ |
H A D | mlx5_ifc.h | 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 501 u8 reserved_at_80[0x10]; 558 u8 smac_15_0[0x10]; 559 u8 ethertype[0x10]; 563 u8 dmac_15_0[0x10]; 577 u8 tcp_sport[0x10]; 578 u8 tcp_dport[0x10]; 587 u8 udp_sport[0x10]; 588 u8 udp_dport[0x10]; 613 u8 source_eswitch_owner_vhca_id[0x10]; [all …]
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6qdl-skov-revc-lt2.dtsi | 69 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 70 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 71 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 72 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 73 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 74 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 75 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 76 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 77 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 78 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 [all …]
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H A D | imx6dl-skov-revc-lt6.dts | 76 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 77 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 78 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 79 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 80 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 81 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 82 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 83 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 84 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 85 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 [all …]
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H A D | imx6qdl-phytec-mira-peb-av-02.dtsi | 77 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 78 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 79 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 81 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 82 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 83 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 84 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 85 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 86 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 87 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 [all …]
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H A D | imx6q-skov-revc-lt6.dts | 98 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 99 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 100 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 101 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 102 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 103 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 104 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 105 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 106 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 107 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 [all …]
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H A D | imx6q-var-mx6customboard.dts | 132 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 133 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 134 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 135 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 136 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 137 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 138 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 139 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 140 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 141 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 [all …]
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/linux/drivers/media/usb/gspca/ |
H A D | sonixj.c | 357 {0xa0, 0x51, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x10}, 358 {0xb0, 0x51, 0x04, 0x08, 0x00, 0x00, 0x00, 0x10}, /* reset */ 360 {0xb0, 0x51, 0x04, 0x00, 0x00, 0x00, 0x00, 0x10}, 362 {0xb0, 0x51, 0x0c, 0xe0, 0x2e, 0x00, 0x00, 0x10}, 363 {0xb0, 0x51, 0x10, 0x02, 0x02, 0x00, 0x00, 0x10}, 364 {0xb0, 0x51, 0x14, 0x0e, 0x0e, 0x00, 0x00, 0x10}, 365 {0xb0, 0x51, 0x1c, 0x00, 0x80, 0x00, 0x00, 0x10}, 366 {0xb0, 0x51, 0x20, 0x01, 0x00, 0x00, 0x00, 0x10}, 368 {0xb0, 0x51, 0x04, 0x04, 0x00, 0x00, 0x00, 0x10}, 370 {0xb0, 0x51, 0x04, 0x01, 0x00, 0x00, 0x00, 0x10}, [all …]
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H A D | nw80x.c | 174 0x00, 0x00, 0x40, 0x10, 0x43, 0x00, 0xb4, 0x01, 0x10, 0x00, 0x4f, 187 0x04, 0x10, 0x00, 0x36, 0x00, 0xd2, 0x00, 0xee, 198 0x04, 0x00, 0x07, 0x01, 0x10, 0x00, 0x00, 0x00, 0x61, 0xc0, 207 0x10, 0x00, 0x40, 0x83, 0x02, 0x20, 0x00, 0x13, 0x00, 0x00, 0x00, 208 0x00, 0x00, 0x00, 0x10, 0x10, 0x10, 0x08, 0x0a, 212 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x10, 0x08, 213 0x03, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10, 0x06, 214 0xf7, 0xee, 0x1c, 0x1c, 0xe9, 0xfc, 0x10, 0x80, 215 0x10, 0x40, 0x40, 0x80, 0x00, 0x05, 0x35, 0x5e, 0x78, 0x8b, 0x99, 223 0x10, 0x80, 0x1d, 0xc3, 0xd2, 0xe2, 0xf1, 0xff, 0x00, 0x00, 0x00, [all …]
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/linux/lib/fonts/ |
H A D | font_6x8.c | 44 0x10, /* 000100 */ 50 0x10, /* 000100 */ 54 0x10, /* 000100 */ 64 0x10, /* 000100 */ 70 0x10, /* 000100 */ 74 0x10, /* 000100 */ 133 0x10, /* 000100 */ 135 0x10, /* 000100 */ 142 0x10, /* 000100 */ 143 0x10, /* 000100 */ [all …]
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H A D | font_6x10.c | 51 0x10, /* 00010000 */ 59 0x10, /* 00010000 */ 63 0x10, /* 00010000 */ 75 0x10, /* 00010000 */ 83 0x10, /* 00010000 */ 87 0x10, /* 00010000 */ 158 0x10, /* 00010000 */ 160 0x10, /* 00010000 */ 169 0x10, /* 00010000 */ 170 0x10, /* 00010000 */ [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/ |
H A D | dcn_2_0_1_sh_mask.h | 70 …_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT 0x10 110 …_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 208 …COND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 224 …TE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 261 …XEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT 0x10 289 …XEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT 0x10 316 …_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT 0x10 321 …_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT 0x10 326 …_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT 0x10 331 …_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT 0x10 [all …]
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H A D | dcn_3_0_2_sh_mask.h | 28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10 33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10 41 …DER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x10 64 …UENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x10 86 …E_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x10 114 …_CONTROL__VGA_SOFT_RESET__SHIFT 0x10 124 …HE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x10 136 …ONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 147 …ONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x10 166 …ERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x10 [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/dce/ |
H A D | dce_8_0_sh_mask.h | 124 #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 152 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 160 …PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 168 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 186 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 192 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 198 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 204 #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x10 210 #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x10 216 #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x10 [all …]
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H A D | dce_11_0_sh_mask.h | 91 #define DCPG_INTERRUPT_STATUS__DCFE2_POWER_UP_INT_OCCURRED_MASK 0x10 123 #define DCPG_INTERRUPT_CONTROL__DCFE1_POWER_UP_INT_MASK_MASK 0x10 148 #define DCPG_INTERRUPT_CONTROL__DCFE4_POWER_UP_INT_MASK__SHIFT 0x10 192 #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x10 220 #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 228 …PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x10 236 #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x10 254 #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x10 260 #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x10 266 #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x10 [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_7_1_sh_mask.h | 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 55 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10 80 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10 109 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10 125 #define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10 150 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10 173 #define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10 206 #define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10 214 #define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10 242 #define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10 [all …]
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