xref: /linux/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira-peb-av-02.dtsi (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Copyright (C) 2018 PHYTEC Messtechnik
4*724ba675SRob Herring * Author: Christian Hemp <c.hemp@phytec.de>
5*724ba675SRob Herring */
6*724ba675SRob Herring
7*724ba675SRob Herring/ {
8*724ba675SRob Herring	display: display0 {
9*724ba675SRob Herring		#address-cells = <1>;
10*724ba675SRob Herring		#size-cells = <0>;
11*724ba675SRob Herring		compatible = "fsl,imx-parallel-display";
12*724ba675SRob Herring		pinctrl-names = "default";
13*724ba675SRob Herring		pinctrl-0 = <&pinctrl_disp0>;
14*724ba675SRob Herring		interface-pix-fmt = "rgb24";
15*724ba675SRob Herring		status = "disabled";
16*724ba675SRob Herring
17*724ba675SRob Herring		port@0 {
18*724ba675SRob Herring			reg = <0>;
19*724ba675SRob Herring
20*724ba675SRob Herring			display0_in: endpoint {
21*724ba675SRob Herring				remote-endpoint = <&ipu1_di0_disp0>;
22*724ba675SRob Herring			};
23*724ba675SRob Herring		};
24*724ba675SRob Herring
25*724ba675SRob Herring		port@1 {
26*724ba675SRob Herring			reg = <1>;
27*724ba675SRob Herring
28*724ba675SRob Herring			display0_out: endpoint {
29*724ba675SRob Herring				remote-endpoint = <&peb_panel_lcd_in>;
30*724ba675SRob Herring			};
31*724ba675SRob Herring		};
32*724ba675SRob Herring	};
33*724ba675SRob Herring
34*724ba675SRob Herring	panel-lcd {
35*724ba675SRob Herring		compatible = "edt,etm0700g0edh6";
36*724ba675SRob Herring		pinctrl-names = "default";
37*724ba675SRob Herring		pinctrl-0 = <&pinctrl_disp0_pwr>;
38*724ba675SRob Herring		power-supply = <&reg_display>;
39*724ba675SRob Herring		enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
40*724ba675SRob Herring		backlight = <&backlight>;
41*724ba675SRob Herring		status = "disabled";
42*724ba675SRob Herring
43*724ba675SRob Herring		port {
44*724ba675SRob Herring			peb_panel_lcd_in: endpoint {
45*724ba675SRob Herring				remote-endpoint = <&display0_out>;
46*724ba675SRob Herring			};
47*724ba675SRob Herring		};
48*724ba675SRob Herring	};
49*724ba675SRob Herring
50*724ba675SRob Herring	reg_display: regulator-peb-display {
51*724ba675SRob Herring		compatible = "regulator-fixed";
52*724ba675SRob Herring		regulator-name = "peb-display";
53*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
54*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
55*724ba675SRob Herring	};
56*724ba675SRob Herring};
57*724ba675SRob Herring
58*724ba675SRob Herring&i2c1 {
59*724ba675SRob Herring	edt_ft5x06: touchscreen@38 {
60*724ba675SRob Herring		compatible = "edt,edt-ft5406";
61*724ba675SRob Herring		pinctrl-names = "default";
62*724ba675SRob Herring		pinctrl-0 = <&pinctrl_edt_ft5x06>;
63*724ba675SRob Herring		reg = <0x38>;
64*724ba675SRob Herring		interrupt-parent = <&gpio3>;
65*724ba675SRob Herring		interrupts = <2 IRQ_TYPE_NONE>;
66*724ba675SRob Herring		status = "disabled";
67*724ba675SRob Herring	};
68*724ba675SRob Herring};
69*724ba675SRob Herring
70*724ba675SRob Herring&ipu1_di0_disp0 {
71*724ba675SRob Herring	remote-endpoint = <&display0_in>;
72*724ba675SRob Herring};
73*724ba675SRob Herring
74*724ba675SRob Herring&iomuxc {
75*724ba675SRob Herring	pinctrl_disp0: disp0grp {
76*724ba675SRob Herring		fsl,pins = <
77*724ba675SRob Herring			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x10
78*724ba675SRob Herring			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x10
79*724ba675SRob Herring			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x10
80*724ba675SRob Herring			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x1b080
81*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x10
82*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x10
83*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x10
84*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x10
85*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x10
86*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x10
87*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x10
88*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x10
89*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x10
90*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x10
91*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x10
92*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x10
93*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x10
94*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x10
95*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x10
96*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x10
97*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x10
98*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x10
99*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x10
100*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x10
101*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x10
102*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x10
103*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x10
104*724ba675SRob Herring			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x10
105*724ba675SRob Herring		>;
106*724ba675SRob Herring	};
107*724ba675SRob Herring
108*724ba675SRob Herring	pinctrl_disp0_pwr: disp0pwrgrp {
109*724ba675SRob Herring		fsl,pins = <
110*724ba675SRob Herring			MX6QDL_PAD_EIM_D22__GPIO3_IO22			0x1b0b0
111*724ba675SRob Herring		>;
112*724ba675SRob Herring	};
113*724ba675SRob Herring
114*724ba675SRob Herring	pinctrl_edt_ft5x06: edtft5x06grp {
115*724ba675SRob Herring		fsl,pins = <
116*724ba675SRob Herring			MX6QDL_PAD_EIM_DA2__GPIO3_IO02			0xb0b1
117*724ba675SRob Herring		>;
118*724ba675SRob Herring	};
119*724ba675SRob Herring};
120