| /linux/tools/perf/pmu-events/arch/s390/cf_z13/ |
| H A D | extended.json | 6 "BriefDescription": "L1D Read-only Exclusive Writes",
13 "BriefDescription": "DTLB1 Writes",
27 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
34 "BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
41 "BriefDescription": "L1D L2D Sourced Writes",
48 "BriefDescription": "ITLB1 Writes",
62 "BriefDescription": "L1I L2I Sourced Writes",
69 "BriefDescription": "TLB2 PTE Writes",
76 "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
83 "BriefDescription": "TLB2 CRSTE Writes",
[all …]
|
| /linux/tools/perf/pmu-events/arch/s390/cf_z14/ |
| H A D | extended.json | 6 "BriefDescription": "L1D Read-only Exclusive Writes",
13 "BriefDescription": "DTLB2 Writes",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
34 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
41 "BriefDescription": "L1D L2D Sourced Writes",
48 "BriefDescription": "ITLB2 Writes",
62 "BriefDescription": "L1I L2I Sourced Writes",
69 "BriefDescription": "TLB2 PTE Writes",
76 "BriefDescription": "TLB2 CRSTE Writes",
111 "BriefDescription": "L1D On-Chip L3 Sourced Writes",
[all …]
|
| /linux/tools/perf/pmu-events/arch/s390/cf_zec12/ |
| H A D | extended.json | 20 "BriefDescription": "L1D L2I Sourced Writes",
27 "BriefDescription": "L1I L2I Sourced Writes",
34 "BriefDescription": "L1D L2D Sourced Writes",
41 "BriefDescription": "DTLB1 Writes",
48 "BriefDescription": "L1D Local Memory Sourced Writes",
55 "BriefDescription": "L1I Local Memory Sourced Writes",
62 "BriefDescription": "L1D Read-only Exclusive Writes",
69 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
76 "BriefDescription": "ITLB1 Writes",
83 "BriefDescription": "TLB2 PTE Writes",
[all …]
|
| /linux/tools/perf/pmu-events/arch/s390/cf_z15/ |
| H A D | extended.json | 6 "BriefDescription": "L1D Read-only Exclusive Writes",
13 "BriefDescription": "DTLB2 Writes",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
34 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
41 "BriefDescription": "L1D L2D Sourced Writes",
48 "BriefDescription": "ITLB2 Writes",
62 "BriefDescription": "L1I L2I Sourced Writes",
69 "BriefDescription": "TLB2 PTE Writes",
76 "BriefDescription": "TLB2 CRSTE Writes",
111 "BriefDescription": "L1D On-Chip L3 Sourced Writes",
[all …]
|
| /linux/tools/perf/pmu-events/arch/s390/cf_z196/ |
| H A D | extended.json | 6 "BriefDescription": "L1D L2 Sourced Writes",
13 "BriefDescription": "L1I L2 Sourced Writes",
41 "BriefDescription": "L1D Off-Book L3 Sourced Writes",
48 "BriefDescription": "L1D On-Book L4 Sourced Writes",
55 "BriefDescription": "L1I On-Book L4 Sourced Writes",
62 "BriefDescription": "L1D Read-only Exclusive Writes",
69 "BriefDescription": "L1D Off-Book L4 Sourced Writes",
76 "BriefDescription": "L1I Off-Book L4 Sourced Writes",
83 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
90 "BriefDescription": "L1D Local Memory Sourced Writes",
[all …]
|
| /linux/drivers/staging/gpib/ni_usb/ |
| H A D | ni_usb_gpib.c | 517 const struct ni_usb_register *writes, int num_writes, in ni_usb_write_registers() argument
538 i += ni_usb_bulk_register_write(&out_data[i], writes[j]); in ni_usb_write_registers()
1065 struct ni_usb_register writes[4]; in ni_usb_request_system_control() local
1072 writes[i].device = NIUSB_SUBDEV_TNT4882; in ni_usb_request_system_control()
1073 writes[i].address = CMDR; in ni_usb_request_system_control()
1074 writes[i].value = SETSC; in ni_usb_request_system_control()
1076 writes[i].device = NIUSB_SUBDEV_TNT4882; in ni_usb_request_system_control()
1077 writes[i].address = nec7210_to_tnt4882_offset(AUXMR); in ni_usb_request_system_control()
1078 writes[i].value = AUX_CIFC; in ni_usb_request_system_control()
1081 writes[i].device = NIUSB_SUBDEV_TNT4882; in ni_usb_request_system_control()
[all …]
|
| /linux/tools/perf/pmu-events/arch/s390/cf_z10/ |
| H A D | extended.json | 6 "BriefDescription": "L1I L2 Sourced Writes",
13 "BriefDescription": "L1D L2 Sourced Writes",
20 "BriefDescription": "L1I L3 Local Writes",
27 "BriefDescription": "L1D L3 Local Writes",
34 "BriefDescription": "L1I L3 Remote Writes",
41 "BriefDescription": "L1D L3 Remote Writes",
48 "BriefDescription": "L1D Local Memory Sourced Writes",
55 "BriefDescription": "L1I Local Memory Sourced Writes",
62 "BriefDescription": "L1D Read-only Exclusive Writes",
76 "BriefDescription": "ITLB1 Writes",
[all …]
|
| /linux/drivers/staging/gpib/agilent_82357a/ |
| H A D | agilent_82357a.c | 214 const struct agilent_82357a_register_pairlet *writes, in agilent_82357a_write_registers() argument
240 out_data[i++] = writes[j].address; in agilent_82357a_write_registers()
241 out_data[i++] = writes[j].value; in agilent_82357a_write_registers()
764 struct agilent_82357a_register_pairlet writes[2]; in agilent_82357a_request_system_control() local
773 writes[i].address = AUXCR; in agilent_82357a_request_system_control()
775 writes[i].value = AUX_RQC; in agilent_82357a_request_system_control()
781 writes[i].address = HW_CONTROL; in agilent_82357a_request_system_control()
782 writes[i].value = a_priv->hw_control_bits; in agilent_82357a_request_system_control()
784 retval = agilent_82357a_write_registers(a_priv, writes, i); in agilent_82357a_request_system_control()
952 struct agilent_82357a_register_pairlet writes[2]; in agilent_82357a_parallel_poll() local
[all …]
|
| /linux/tools/perf/scripts/perl/ |
| H A D | rw-by-pid.pl | 22 my %writes;
58 $writes{$common_pid}{errors}{$ret}++;
68 $writes{$common_pid}{bytes_written} += $count;
69 $writes{$common_pid}{total_writes}++;
70 $writes{$common_pid}{comm} = $common_comm;
119 "# writes", "bytes_written");
123 foreach my $pid (sort { ($writes{$b}{bytes_written} || 0) <=>
124 ($writes{$a}{bytes_written} || 0)} keys %writes) {
125 my $comm = $writes{$pid}{comm} || "";
126 my $total_writes = $writes{$pid}{total_writes} || 0;
[all …]
|
| H A D | rwtop.pl | 28 my %writes;
75 $writes{$common_pid}{errors}{$ret}++;
87 $writes{$common_pid}{bytes_written} += $count;
88 $writes{$common_pid}{total_writes}++;
89 $writes{$common_pid}{comm} = $common_comm;
156 "# writes", "bytes_written");
160 foreach my $pid (sort { ($writes{$b}{bytes_written} || 0) <=>
161 ($writes{$a}{bytes_written} || 0)} keys %writes) {
162 my $comm = $writes{$pid}{comm} || "";
163 my $total_writes = $writes{$pid}{total_writes} || 0;
[all …]
|
| H A D | rw-by-file.pl | 26 my %writes;
45 $writes{$fd}{bytes_written} += $count;
46 $writes{$fd}{total_writes}++;
66 printf("%6s %10s %10s\n", "fd", "# writes", "bytes_written");
69 foreach my $fd (sort {$writes{$b}{bytes_written} <=>
70 $writes{$a}{bytes_written}} keys %writes) {
71 my $total_writes = $writes{$fd}{total_writes};
72 my $bytes_written = $writes{$fd}{bytes_written};
|
| /linux/include/dt-bindings/memory/ |
| H A D | tegra186-mc.h | 129 /* PCIE writes */
131 /* High-definition audio (HDA) writes */
133 /* Writes from Cortex-A9 4 CPU cores via the L2 cache */
135 /* SATA writes */
145 /* XUSB_HOST writes */
149 /* XUSB_DEV writes */
157 /* 3D, ltcx writes instance 0 */
183 /* Audio Processing (APE) engine writes */
193 /* ETR writes */
201 /* 3D, ltcx writes instance 1 */
|
| /linux/Documentation/driver-api/md/ |
| H A D | raid5-cache.rst | 19 In both modes, all writes to the array will hit cache disk first. This means
28 disks and it's possible the writes don't hit all RAID disks yet before the
53 write. For non-full-stripe writes, MD must read old data before the new parity
54 can be calculated. These synchronous reads hurt write throughput. Some writes
90 order in which MD writes data to cache disk and RAID disks. Specifically, in
91 write-through mode, MD calculates parity for IO data, writes both IO data and
92 parity to the log, writes the data and parity to RAID disks after the data and
96 In write-back mode, MD writes IO data to the log and reports IO completion. The
110 they are discarded too. MD then loads valid data and writes them to RAID disks
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-block-bcache | 55 Sum of all reads and writes that have bypassed the cache (due
64 writes will be buffered in the cache. When off, caching is in
65 writethrough mode; reads and writes will be added to the
74 used to buffer writes until it is mostly full, at which point
75 writes transparently revert to writethrough mode. Intended only
94 place and reducing total number of writes sent to the backing
102 switched on and off. In synchronous mode all writes are ordered
104 if disabled bcache will not generally wait for writes to
156 For a cache, sum of all btree writes in human readable units.
|
| /linux/Documentation/driver-api/ |
| H A D | io_ordering.rst | 2 Ordering I/O writes to memory-mapped addresses
6 platforms, driver writers are responsible for ensuring that I/O writes to
9 chipset to flush pending writes to the device before any reads are posted. A
12 subsequent writes to I/O space arrived only after all prior writes (much like a
50 pending writes before actually posting the read to the chipset, preventing
|
| H A D | device-io.rst | 76 are burned by the fact that PCI bus writes are posted asynchronously. A
78 writes have occurred in the specific cases the author cares. This kind
107 outstanding DMA writes from that bus, since for some devices the result of
110 next readb() call has no relation to any previous DMA writes
176 Note that posted writes are not strictly ordered against a spinlock, see
305 * Uncached - CPU-side caches are bypassed, and all reads and writes are handled
313 * No repetition - The CPU may not issue multiple reads or writes for a single
316 being issued to the device, and multiple writes are not combined into larger
317 writes. This may or may not be enforced when using __raw I/O accessors or
323 On many platforms and buses (e.g. PCI), writes issued through ioremap()
[all …]
|
| /linux/lib/ |
| H A D | Kconfig.kcsan | 201 particular reordered writes.
216 bool "Assume that plain aligned writes up to word size are atomic"
220 Assume that plain aligned writes up to word size are atomic by
224 writes up to word size: conflicts between marked reads and plain
225 aligned writes up to word size will not be reported as data races;
226 notice that data races between two conflicting plain aligned writes
235 writes will never be reported as a data race, however, will cause
236 plain reads and marked writes to result in "unknown origin" reports.
242 accesses, conflicting marked atomic reads and plain writes will not
244 due to two conflicting plain writes will be reported (aligned and
|
| /linux/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| H A D | uncore-io.json | 433 "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
445 "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
457 "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
469 "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
481 "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
493 "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
505 "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
517 "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
542 "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
555 "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| H A D | uncore-io.json | 353 "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
365 "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
377 "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
389 "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
401 "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
413 "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1",
425 "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1",
437 "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3",
462 "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
475 "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes
[all...] |
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | cache.json | 114 …ch cycle where the core is in write streaming mode and is not allocating writes into the L2 cache",
117 …ach cycle where the core is in write streaming mode and is not allocating writes into the L2 cache"
126 …ch cycle where the core is in write streaming mode and is not allocating writes into the L1 data c…
129 …ch cycle where the core is in write streaming mode and is not allocating writes into the L1 data c…
132 …ch cycle where the core is in write streaming mode and is not allocating writes into the L3 cache",
135 …ach cycle where the core is in write streaming mode and is not allocating writes into the L3 cache"
138 …ch cycle where the core is in write streaming mode and is not allocating writes into the system ca…
141 …ch cycle where the core is in write streaming mode and is not allocating writes into the system ca…
|
| /linux/Documentation/admin-guide/device-mapper/ |
| H A D | log-writes.rst | 2 dm-log-writes
24 the FLUSH request completes we log all of the WRITEs and then the FLUSH. Only
25 completed WRITEs, at the time the REQ_PREFLUSH is issued, are added in order to
59 log-writes <dev_path> <log_dev_path>
93 Every log has a mark at the end labeled "dm-log-writes-end".
99 It can be found here: https://github.com/josefbacik/log-writes
107 TABLE="0 $(blockdev --getsz /dev/sdb) log-writes /dev/sdb /dev/sdc"
127 TABLE="0 $(blockdev --getsz /dev/sdb) log-writes /dev/sdb /dev/sdc"
|
| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | uncore-io.json | 13 …die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugge…
29 …die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugge…
372 …e. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0",
385 …e. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1",
398 …e. Includes all requests initiated by the main die, including reads and writes. : x16 card plugge…
411 …e. Includes all requests initiated by the main die, including reads and writes. : x4 card is plug…
424 …e. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged…
437 …e. Includes all requests initiated by the main die, including reads and writes. : x4 card is plug…
450 …e. Includes all requests initiated by the main die, including reads and writes. : x16 card plugge…
463 …e. Includes all requests initiated by the main die, including reads and writes. : x4 card is plug…
[all …]
|
| H A D | uncore-memory.json | 400 "BriefDescription": "Pre-charge for writes",
552 … is used to schedule write out to the memory controller and to track the writes. Requests allocat…
563 … is used to schedule write out to the memory controller and to track the writes. Requests allocat…
573 … is used to schedule write out to the memory controller and to track the writes. Requests allocat…
583 … is used to schedule write out to the memory controller and to track the writes. Requests allocat…
593 …writes. Requests allocate into the WPQ soon after they enter the memory controller, and need cred…
602 …writes. Requests allocate into the WPQ soon after they enter the memory controller, and need cred…
612 …writes and reads to pass up other writes to different addresses. Before a read or a write is issu…
623 …writes and reads to pass up other writes to different addresses. Before a read or a write is issu…
634 …writes and reads to pass up other writes to different addresses. Before a read or a write is issu…
[all …]
|
| /linux/Documentation/filesystems/ |
| H A D | fuse-io.rst | 17 In direct-io mode the page cache is completely bypassed for reads and writes.
23 after any writes to the file. All mmap modes are supported.
25 The cached mode has two sub modes controlling how writes are handled. The
32 uncached, but fully written pages). No READ requests are ever sent for writes,
35 In writeback-cache mode (enabled by the FUSE_WRITEBACK_CACHE flag) writes go to
|
| /linux/arch/mips/include/asm/vdso/ |
| H A D | processor.h | 12 * Loongson-3's SFB (Store-Fill-Buffer) may buffer writes indefinitely when a
13 * tight read loop is executed, because reads take priority over writes & the
14 * hardware (incorrectly) doesn't ensure that writes will eventually occur.
17 * flush from cpu_relax() such that any pending writes will become visible as
|