| /linux/Documentation/w1/masters/ |
| H A D | w1-uart.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Kernel driver w1-uart
11 -----------
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 …g a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a-u…
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
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| /linux/drivers/w1/slaves/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # 1-wire slaves configuration
6 menu "1-wire Slaves"
11 Say Y here if you want to connect 1-wire thermal sensors to your
12 wire.
17 Say Y here if you want to connect 1-wire
18 simple 64bit memory rom(ds2401/ds2411/ds1990*) to your wire.
23 Say Y or M here if you want to use a DS2405 1-wire
24 single-channel addressable switch.
25 This device can also work as a single-channel
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| /linux/Documentation/devicetree/bindings/w1/ |
| H A D | w1-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/w1/w1-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART 1-Wire Bus
10 - Christoph Winklhofer <cj.winklhofer@gmail.com>
13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
14 to create the 1-Wire timing patterns.
16 The UART peripheral must support full-duplex and operate in open-drain
18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
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| H A D | amd,axi-1wire-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AMD AXI 1-wire bus host for programmable logic
10 - Kris Chaplin <kris.chaplin@amd.com>
14 const: amd,axi-1wire-host
26 - compatible
27 - reg
28 - clocks
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| /linux/drivers/w1/masters/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # 1-wire bus master configuration
6 menu "1-wire Bus Masters"
9 tristate "AMD AXI 1-wire bus host"
11 Say Y here is you want to support the AMD AXI 1-wire IP core.
13 correctly timed 1 wire transactions without relying on GPIO timing
20 tristate "Matrox G400 transport layer for 1-wire"
23 Say Y here if you want to communicate with your 1-wire devices
30 tristate "DS2490 USB <-> W1 transport layer for 1-wire"
33 Say Y here if you want to have a driver for DS2490 based USB <-> W1 bridges,
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| H A D | amd_axi_w1.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * amd_axi_w1 - AMD 1Wire programmable logic bus host driver
5 * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
23 /* 1-wire AMD IP definition */
68 * amd_axi_w1_wait_irq_interruptible_timeout() - Wait for IRQ with timeout.
73 * Return: %0 - OK, %-EINTR - Interrupted, %-EBUSY - Timed out
81 iowrite32(IRQ, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG); in amd_axi_w1_wait_irq_interruptible_timeout()
82 ret = wait_event_interruptible_timeout(amd_axi_w1_local->wait_queue, in amd_axi_w1_wait_irq_interruptible_timeout()
83 atomic_read(&amd_axi_w1_local->flag) != 0, in amd_axi_w1_wait_irq_interruptible_timeout()
86 dev_err(amd_axi_w1_local->dev, "Wait IRQ Interrupted\n"); in amd_axi_w1_wait_irq_interruptible_timeout()
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | intel,ce4100-lapic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
32 const: intel,ce4100-lapic
37 interrupt-controller: true
39 '#interrupt-cells':
42 intel,virtual-wire-mode:
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| H A D | arm,gic-v5-iwb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (IWB)
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
20 GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible
21 for translating wire signals into interrupt messages to the GICv5 ITS.
24 - $ref: /schemas/interrupt-controller.yaml#
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| /linux/Documentation/peci/ |
| H A D | peci.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
13 controller is acting as a PECI originator and the processor - as
15 PECI can be used in both single processor and multiple-processor based
24 PECI Wire
25 ---------
27 PECI Wire interface uses a single wire for self-clocking and data
28 transfer. It does not require any additional control lines - the
29 physical layer is a self-clocked one-wire bus signal that begins each
32 value is logic '0' or logic '1'. PECI Wire also includes variable data
35 For PECI Wire, each processor package will utilize unique, fixed
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| /linux/arch/sh/mm/ |
| H A D | tlb-urb.c | 2 * arch/sh/mm/tlb-urb.c
4 * TLB entry wiring helpers for URB-equipped parts.
18 * Load the entry for 'addr' into the TLB and wire the entry.
32 * Make sure we're not trying to wire the last TLB entry slot. in tlb_wire_entry()
34 BUG_ON(!--urb); in tlb_wire_entry()
39 * Insert this entry into the highest non-wired TLB slot (via in tlb_wire_entry()
49 /* ... and wire it up. */ in tlb_wire_entry()
64 * It should also be noted that it is not possible to wire and unwire
65 * TLB entries in an arbitrary order. If you wire TLB entry N, followed
67 * respect, it works like a stack or LIFO queue.
|
| /linux/drivers/w1/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Dallas's 1-wire support"
6 Dallas' 1-wire bus is useful to connect slow 1-pin devices
12 will be called wire.
22 information see <file:Documentation/driver-api/connector.rst>.
24 1. Events. They are generated each time new master or slave device found
25 either due to automatic or requested search.
|
| /linux/Documentation/devicetree/bindings/display/panel/ |
| H A D | tpo,tpg110.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Thierry Reding <thierry.reding@gmail.com>
17 and other properties, and has a control interface over 3WIRE
20 self-describing.
22 +--------+
23 SPI -> | TPO | -> physical display
24 RGB -> | TPG110 |
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| /linux/Documentation/iio/ |
| H A D | ad4000.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
41 * `AD7988-1 <https://www.analog.com/AD7988-1>`_
42 * `AD7988-5 <https://www.analog.com/AD7988-5>`_
45 ------------------
50 CS mode, 3-wire turbo mode
53 Datasheet "3-wire" mode is what most resembles standard SPI connection which,
56 "CS Mode, 3-Wire Turbo Mode" connection in datasheets.
57 NOTE: The datasheet definition of 3-wire mode for the AD4000 series is NOT the
58 same of standard spi-3wire mode.
62 Omit the ``adi,sdi-pin`` property in device tree to select this mode.
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| /linux/include/linux/platform_data/ |
| H A D | usb-omap1.h | 15 * - "A" connector (rectagular)
17 * - "B" connector (squarish) or "Mini-B"
19 * - "Mini-AB" connector (very similar to Mini-B)
20 * ... for OTG use as device OR host, initialize "otg"
24 u8 otg; /* port number, 1-based: usb1 == 2 */
35 * 2 == usb0-only, using internal transceiver
36 * 3 == 3 wire bidirectional
37 * 4 == 4 wire bidirectional
38 * 6 == 6 wire unidirectional (or TLL)
|
| /linux/Documentation/driver-api/gpio/ |
| H A D | intro.rst | 17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
20 represents a bit connected to a particular pin, or "ball" on Ball Grid Array
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
30 also "GPIO Expander" chips that connect using the I2C or SPI serial buses.
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
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| /linux/include/linux/ |
| H A D | w1.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * struct w1_reg_num - broken out slave device id
49 * struct w1_slave - holds a single slave device on the bus
51 * @owner: Points to the one wire "wire" kernel module.
84 * struct w1_bus_master - operations available on a bus master
89 * @return the level read (0 or 1)
93 * @touch_bit: the lowest-level function for devices that really support the
94 * 1-wire protocol.
95 * touch_bit(0) = write-0 cycle
96 * touch_bit(1) = write-1 / read cycle
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| /linux/Documentation/w1/ |
| H A D | w1-generic.rst | 2 Introduction to the 1-wire (w1) subsystem
5 The 1-wire bus is a simple master-slave bus that communicates via a single
6 signal wire (plus ground, so two wires).
18 - DS9490 usb device
19 - W1-over-GPIO
20 - DS2482 (i2c to w1 bridge)
21 - Emulated devices, such as a RS232 converter, parallel port adapter, etc
25 ------------------------------
29 - sysfs entries for that w1 master are created
30 - the w1 bus is periodically searched for new slave devices
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| /linux/Documentation/devicetree/bindings/input/touchscreen/ |
| H A D | ti,am3359-tsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/touchscreen/ti,am3359-tsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 const: ti,am3359-tsc
17 description: Wires refer to application modes i.e. 4/5/8 wire touchscreen
22 ti,x-plate-resistance:
26 ti,coordinate-readouts:
36 ti,wire-config:
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| /linux/sound/ppc/ |
| H A D | snd_ps3_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
39 * three wire serial
73 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
75 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
92 corresponding bit in PS3_AUDIO_INTR_0. The resulting bits are OR'd together
96 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
98 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
106 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
108 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
125 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+
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| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | awinic,aw8738.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
14 (set using one-wire pulse control). The mode configures the speaker-guard
18 - $ref: dai-common.yaml#
24 mode-gpios:
26 GPIO used for one-wire pulse control. The pin is typically called SHDN
27 (active-low), but this is misleading since it is actually more than
32 description: Operation mode (number of pulses for one-wire pulse control)
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| /linux/Documentation/devicetree/bindings/rtc/ |
| H A D | nxp,pcf85063.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
15 - microcrystal,rv8063
16 - microcrystal,rv8263
17 - nxp,pcf85063
18 - nxp,pcf85063a
19 - nxp,pcf85063tp
20 - nxp,pca85073a
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| /linux/drivers/bluetooth/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
36 kernel or say M to compile it as module (btusb).
102 kernel or say M to compile it as module (btsdio).
118 kernel or say M to compile it as module (hci_uart).
188 bool "Three-wire UART (H5) protocol support"
192 The HCI Three-wire UART Transport Layer makes it possible to
194 Three-wire UART Transport Layer assumes that the UART
195 communication may have bit errors, overrun errors or burst
198 Say Y here to compile support for Three-wire UART protocol.
235 The Realtek protocol support enables Bluetooth HCI over 3-Wire
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| /linux/Documentation/hwmon/ |
| H A D | lm85.rst | 8 Prefix: 'lm85b' or 'lm85c'
79 - Philip Pokorny <ppokorny@penguincomputing.com>,
80 - Frodo Looijaard <frodol@dds.nl>,
81 - Richard Barrington <rich_b_nz@clear.net.nz>,
82 - Margit Schubert-While <margitsw@t-online.de>,
83 - Justin Thiessen <jthiessen@penguincomputing.com>
86 -----------
92 The LM85 uses the 2-wire interface compatible with the SMBUS 2.0
94 temperatures and five (5) voltages. It has four (4) 16-bit counters for
107 423 or socket 478 package. They can also measure temperature using a
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| /linux/Documentation/sound/soc/ |
| H A D | dai.rst | 12 AC97 is a five wire interface commonly found on many PC sound cards. It is
26 I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
35 I2S has several different operating modes:-
50 PCM is another 4 wire interface, very similar to I2S, which can support a more
58 Common PCM operating modes:-
|
| /linux/include/linux/mfd/ |
| H A D | mxs-lradc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Freescale MXS Low Resolution Analog-to-Digital Converter driver
110 #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
117 * and/or touch-buttons and generic LRADC block. Therefore when using
121 * CH0 -- Touch button #0
122 * CH1 -- Touch button #1
123 * CH2 -- Touch screen XPUL
124 * CH3 -- Touch screen YPLL
125 * CH4 -- Touch screen XNUL
126 * CH5 -- Touch screen YNLR
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|