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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remotepro
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7-ipu-dsp-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
11 mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
18 mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
25 ti,timers = <&timer3>;
26 ti,watchdog-timers = <&timer4>, <&timer9>;
31 ti,timers = <&timer11>;
32 ti,watchdog-timers = <&timer7>, <&timer8>;
37 ti,timers = <&timer5>;
38 ti,watchdog-timers = <&timer10>;
H A Domap5-uevm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
7 #include "omap5-board-common.dtsi"
11 compatible = "ti,omap5-uevm", "ti,omap5";
18 reserved-memory {
19 #address-cells = <2>;
20 #size-cells = <2>;
23 dsp_memory_region: dsp-memory@95000000 {
24 compatible = "shared-dma-pool";
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H A Ddra74-ipu-dsp-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include "dra7-ipu-dsp-common.dtsi"
9 mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
16 ti,timers = <&timer6>;
17 ti,watchdog-timers = <&timer13>;
/freebsd/share/man/man4/
H A Dwdatwd.41 .\"-
30 .Nd device driver for the ACPI WDAT based watchdog interrupt timer
35 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
49 .Xr watchdog 4
50 support for the watchdog interrupt timer in ACPI WDAT (Watchdog Action Table).
56 The following read-only
59 .Bl -tag -width indent
61 The status of the watchdog timer. 0 if not running, or 1 if running.
63 The current value of the watchdog timeout in millisecond.
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H A Damdsbwd.41 .\"-
31 .Nd device driver for the AMD southbridge watchdog timers
36 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
50 .Xr watchdog 4
51 support for the watchdog timers present on
58 .Bl -bullet -compact
64 AMD FCHs integrated into Family 15h Models 60h-6Fh, 70h-7Fh Processors
66 AMD FCHs integrated into Family 16h Models 00h-0Fh, 30h-3Fh Processors
69 .Xr watchdog 4 ,
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/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dti,davinci-timer.txt3 This document provides bindings for the 64-bit timer in the DaVinci
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
6 timers, each half can operate in conjunction (chain mode) or independently
9 The timer is a free running up-counter and can generate interrupts when the
12 Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
13 watchdog timers.
17 - compatible : should be "ti,da830-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupts generated by the timer.
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H A Dqcom,msm-timer.txt5 - compatible : Should at least contain "qcom,msm-timer". More specific
6 properties specify which subsystem the timers are paired with.
8 "qcom,kpss-timer" - krait subsystem
9 "qcom,scss-timer" - scorpion subsystem
11 - interrupts : Interrupts for the debug timer, the first general purpose
13 optionally as well, 2 watchdog interrupts, in that order.
15 - reg : Specifies the base address of the timer registers.
17 - clocks: Reference to the parent clocks, one per output clock. The parents
20 - clock-names: The name of the clocks as free-form strings. They should be in
23 - clock-frequency : The frequency of the debug timer and the general purpose
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/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Datmel-wdt.txt1 * Atmel Watchdog Timers
3 ** at91sam9-wdt
6 - compatible: must be "atmel,at91sam9260-wdt".
7 - reg: physical base address of the controller and length of memory mapped
9 - clocks: phandle to input clock.
12 - timeout-sec: contains the watchdog timeout in seconds.
13 - interrupts : Should contain WDT interrupt.
14 - atmel,max-heartbeat-sec : Should contain the maximum heartbeat value in
17 - atmel,min-heartbeat-sec : Should contain the minimum heartbeat value in
18 seconds. This value must be smaller than the max-heartbeat-sec value.
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H A Dralink,rt2880-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/ralink,rt2880-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink Watchdog Timers
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 - $ref: watchdog.yaml#
17 const: ralink,rt2880-wdt
32 - compatible
33 - reg
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H A Dmediatek,mt7621-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/mediatek,mt7621-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink Watchdog Timers
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 - $ref: watchdog.yaml#
17 const: mediatek,mt7621-wdt
29 - compatible
30 - reg
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H A Dmaxim,max63xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/maxi
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H A Datmel,at91sam9-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/watchdog/atmel,at91sam9-wdt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Atmel Watchdog Timers
11 - Eugen Hristev <eugen.hristev@microchip.com>
15 const: atmel,at91sam9260-wdt
26 atmel,max-heartbeat-sec:
32 atmel,min-heartbeat-sec:
35 must be smaller than the max-heartbeat-sec value. It is used to
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H A Dmt7621-wdt.txt1 Ralink Watchdog Timers
4 - compatible: must be "mediatek,mt7621-wdt"
5 - reg: physical base address of the controller and length of the register range
9 watchdog@100 {
10 compatible = "mediatek,mt7621-wdt";
H A Drt2880-wdt.txt1 Ralink Watchdog Timers
4 - compatible: must be "ralink,rt2880-wdt"
5 - reg: physical base address of the controller and length of the register range
8 - interrupts: Specify the INTC interrupt number
12 watchdog@120 {
13 compatible = "ralink,rt2880-wdt";
16 interrupt-parent = <&intc>;
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dbrcm,twd.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom's Timer-Watchdog (aka TWD)
10 - Rafał Miłecki <rafal@milecki.pl>
13 Broadcom has a Timer-Watchdog block used in multiple SoCs (e.g., BCM4908,
15 registers layout). This block consists of: timers, watchdog and optionally a
21 - enum:
22 - brcm,bcm4908-twd
23 - brcm,bcm7038-twd
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
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H A Dmips-gic.txt4 It also supports local (per-processor) interrupts and software-generated
5 interrupts which can be used as IPIs. The GIC also includes a free-running
6 global timer, per-CPU count/compare timers, and a watchdog.
9 - compatible : Should be "mti,gic".
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
13 - The first cell is the type of interrupt, local or shared.
14 See <include/dt-bindings/interrupt-controller/mips-gic.h>.
15 - The second cell is the GIC interrupt number.
16 - The third cell encodes the interrupt flags.
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/freebsd/usr.sbin/uhsoctl/
H A Duhsoctl.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2008-2009 Fredrik Lindberg
103 #define FLG_WATCHDOG 0x20 /* Watchdog enabled */
104 #define FLG_WDEXP 0x40 /* Watchdog expired */
111 time_t watchdog; member
176 struct timers { struct
191 static struct timers timers; argument
198 tmr_run(struct timers *tmrs) in tmr_run()
202 te = TAILQ_FIRST(&tmrs->head); in tmr_run()
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/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dkeystone-reset.txt6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
26 - ti,soft-reset: Boolean option indicating soft reset.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
40 pllctrl: pll-controller@2310000 {
41 compatible = "ti,keystone-pllctrl", "syscon";
45 devctrl: device-state-control@2620000 {
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/freebsd/share/man/man9/
H A Dhardclock.935 .Nd real-time timer
58 argument is non-zero when
64 .Bl -bullet -offset indent
67 corresponding timers, if they are activated, and generate
73 Increment the time-of-day, taking care of any
98 .Xr watchdog 9
116 .Xr watchdog 9
/freebsd/usr.sbin/acpi/acpidump/
H A Dacpidump.8101 .Bl -tag -offset indent -width 12345 -compact
125 Describes the high precision timers in the system.
135 .It MCFG PCI Express Memory-mapped Configuration
157 .It WDDT Watchdog Timer Description Table
158 Information about how to manage watchdog timers in the system.
168 the DSDT consists of free-formatted AML data.
172 .Bl -tag -width indent
207 .Bl -tag -width /dev/mem
213 .Bd -literal -offset indent
214 # acpidump -dt | gzip -c9 > my_computer.asl.gz
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/freebsd/sys/arm64/apple/
H A Dapple_wdog.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <sys/watchdog.h>
69 #define READ(_sc, _r) bus_space_read_4((_sc)->bst, (_sc)->bsh, (_r))
70 #define WRITE(_sc, _r, _v) bus_space_write_4((_sc)->bst, (_sc)->bsh, (_r), (_v))
97 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in apple_wdog_probe()
100 device_set_desc(dev, "Apple Watchdog"); in apple_wdog_probe()
112 sc->dev = dev; in apple_wdog_attach()
115 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); in apple_wdog_attach()
116 if (sc->res == NULL) { in apple_wdog_attach()
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/freebsd/sys/arm/mv/
H A Dtimer.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
43 #include <sys/watchdog.h>
62 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */
92 { -1, 0 }
97 {"marvell,armada-380-timer", MV_NONE },
98 {"marvell,armada-xp-timer", MV_TMR | MV_WDT },
152 {"marvell,armada-xp-timer", (uintptr_t)&timer_armadaxp_config },
172 if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE) in mv_timer_probe()
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/freebsd/sys/arm/arm/
H A Dmpcore_timer.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
35 * The ARM Cortex-A9 core can support a global timer plus a private and
36 * watchdog timer per core. This driver reserves memory and interrupt
40 * The timecount timer uses the global 64-bit counter, whereas the
41 * per-CPU eventtimer uses the private 32-bit counters.
44 * REF: ARM Cortex-A9 MPCore, Technical Reference Manual (rev. r2p2)
56 #include <sys/watchdog.h>
71 /* Private (per-CPU) timer register map */
114 #define tmr_prv_read_4(sc, reg) bus_read_4((sc)->prv_mem, reg)
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