| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | rohm,bd9576-pmic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd9576-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 powering the R-Car series processors.
16 monitoring. A watchdog logic with slow ping/windowed modes is also included.
21 - rohm,bd9576
22 - rohm,bd9573
32 rohm,vout1-en-low:
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| H A D | st,stpmic1.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - pascal Paillet <p.paillet@foss.st.com>
24 "#interrupt-cells":
27 interrupt-controller: true
36 const: st,stpmic1-onkey
40 - description: onkey-falling, happens when onkey is pressed. IT_PONKEY_F of pmic
41 - description: onkey-rising, happens when onkey is released. IT_PONKEY_R of pmic
43 interrupt-names:
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| /freebsd/sys/contrib/device-tree/Bindings/watchdog/ |
| H A D | atmel-sama5d4-wdt.txt | 1 * Atmel SAMA5D4 Watchdog Timer (WDT) Controller
4 - compatible: "atmel,sama5d4-wdt" or "microchip,sam9x60-wdt"
5 - reg: base physical address and length of memory mapped region.
8 - timeout-sec: watchdog timeout value (in seconds).
9 - interrupts: interrupt number to the CPU.
10 - atmel,watchdog-type: should be "hardware" or "software".
11 "hardware": enable watchdog fault reset. A watchdog fault triggers
12 watchdog reset.
13 "software": enable watchdog fault interrupt. A watchdog fault asserts
14 watchdog interrupt.
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| H A D | xlnx,xps-timebase-wdt.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI/PLB softcore and window Watchdog Timer
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
22 - $ref: watchdog.yaml#
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| H A D | atmel,sama5d4-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/atmel,sama5d4-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel SAMA5D4 Watchdog Timer (WDT) Controller
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - atmel,sama5d4-wdt
20 - microchip,sam9x60-wdt
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| H A D | of-xilinx-wdt.txt | 1 Xilinx AXI/PLB soft-core watchdog Device Tree Bindings
2 ---------------------------------------------------------
5 - compatible : Should be "xlnx,xps-timebase-wdt-1.00.a" or
6 "xlnx,xps-timebase-wdt-1.01.a".
7 - reg : Physical base address and size
10 - clocks : Input clock specifier. Refer to common clock
12 - clock-frequency : Frequency of clock in Hz
13 - xlnx,wdt-enable-once : 0 - Watchdog can be restarted
14 1 - Watchdog can be enabled just once
15 - xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
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| H A D | men-a021-wdt.txt | 1 Bindings for MEN A21 Watchdog device connected to GPIO lines
4 - compatible: "men,a021-wdt"
5 - gpios: Specifies the pins that control the Watchdog, order:
6 1: Watchdog enable
7 2: Watchdog fast-mode
8 3: Watchdog trigger
9 4: Watchdog reset cause bit 0
10 5: Watchdog reset cause bit 1
11 6: Watchdog reset cause bit 2
14 - None
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| H A D | sprd,sp9860-wdt.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/sprd,sp9860-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SP9860 watchdog timer
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 - $ref: watchdog.yaml#
19 const: sprd,sp9860-wdt
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| H A D | aspeed-wdt.txt | 1 Aspeed Watchdog Timer
4 - compatible: must be one of:
5 - "aspeed,ast2400-wdt"
6 - "aspeed,ast2500-wdt"
7 - "aspeed,ast2600-wdt"
9 - reg: physical base address of the controller and length of memory mapped
14 - aspee
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| H A D | st_lpc_wdt.txt | 1 STMicroelectronics Low Power Controller (LPC) - Watchdog
4 LPC currently supports Watchdog OR Real Time Clock OR Clocksource
7 [See: ../rtc/rtc-st-lpc.txt for RTC options]
8 [See: ../timer/st,stih407-lpc for Clocksource options]
12 - compatible : Should be: "st,stih407-lpc"
13 - reg : LPC registers base address + size
14 - interrupts : LPC interrupt line number and associated flags
15 - clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
16 - st,lpc-mode : The LPC can run either one of three modes:
22 Required properties [watchdog mode]
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| H A D | sprd-wdt.txt | 1 Spreadtrum SoCs Watchdog timer
4 - compatible : Should be "sprd,sp9860-wdt".
5 - reg : Specifies base physical address and size of the registers.
6 - interrupts : Exactly one interrupt specifier.
7 - timeout-sec : Contain the default watchdog timeout in seconds.
8 - clock-names : Contain the input clock names.
9 - clocks : Phandles to input clocks.
12 watchdog: watchdog@40310000 {
13 compatible = "sprd,sp9860-wdt";
16 timeout-sec = <12>;
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| H A D | marvel.txt | 1 * Marvell Orion Watchdog Time
5 - Compatibility : "marvell,orion-wdt"
6 "marvell,armada-370-wdt"
7 "marvell,armada-xp-wdt"
8 "marvell,armada-375-wdt"
9 "marvell,armada-380-wdt"
11 - reg : Should contain two entries: first one with the
13 rstout enable address.
15 For "marvell,armada-375-wdt" and "marvell,armada-380-wdt":
17 - reg : A third entry is mandatory and should contain the
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| /freebsd/sys/arm/ti/ |
| H A D | ti_wdt.h | 1 /*-
30 #define TI_WDT_WIDR 0x00 /* Watchdog Identification Register */
31 #define TI_WDT_WDSC 0x10 /* Watchdog System Control Register */
32 #define TI_WDT_WDST 0x14 /* Watchdog Status Register */
33 #define TI_WDT_WISR 0x18 /* Watchdog Interrupt Status Register */
34 #define TI_WDT_WIER 0x1c /* Watchdog Interrupt Enable Register */
35 #define TI_WDT_WCLR 0x24 /* Watchdog Control Register */
36 #define TI_WDT_WCRR 0x28 /* Watchdog Counter Register */
37 #define TI_WDT_WLDR 0x2c /* Watchdog Load Register */
38 #define TI_WDT_WTGR 0x30 /* Watchdog Trigger Register */
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| /freebsd/sys/dev/viawd/ |
| H A D | viawd.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #include <sys/watchdog.h>
45 #define viawd_read_4(sc, off) bus_read_4((sc)->wd_res, (off))
47 bus_write_4((sc)->wd_res, (off), (val))
50 { DEVICEID_VT8251, "VIA VT8251 watchdog timer" },
51 { DEVICEID_CX700, "VIA CX700 watchdog timer" },
52 { DEVICEID_VX800, "VIA VX800 watchdog timer" },
53 { DEVICEID_VX855, "VIA VX855 watchdog timer" },
54 { DEVICEID_VX900, "VIA VX900 watchdog timer" },
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| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | richtek,rt5759-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rt5759-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
13 The RT5759 is a high-performance, synchronous step-down DC-DC converter that
15 voltage can be programmable with I2C controlled 7-Bit VID.
18 https://www.richtek.com/assets/product_file/RT5759/DS5759-00.pdf
23 - richtek,rt5759
24 - richtek,rt5759a
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| /freebsd/sys/dev/amdsbwd/ |
| H A D | amdsbwd.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx
34 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG)
35 …* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.…
36 * - AMD SB700/710/750 Register Reference Guide (RRG)
38 * - AMD SB700/710/750 Register Programming Requirements (RPR)
40 * - AMD SB800-Series Southbridges Register Reference Guide (RRG)
42 * Please see the following for Watchdog Resource Table specification:
43 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT)
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| /freebsd/sys/dev/wbwd/ |
| H A D | wbwd.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Support for Winbond watchdog.
38 * the watchdog functions and possibly others poking the registers at the same
50 #include <sys/watchdog.h>
66 #define WB_LDN_REG_LDN8 0x08 /* GPIO 2, Watchdog */
69 * LDN8 (GPIO 2, Watchdog) specific registers and options.
75 /* CRF5: Watchdog scale, P20. Mapped to reg_1. */
81 /* CRF6: Watchdog Timeout (0 == off). Mapped to reg_timeout. */
84 /* CRF7: Watchdog mouse, keyb, force, .. Mapped to reg_2. */
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| /freebsd/share/man/man4/ |
| H A D | watchdog.4 | 1 .\" Copyright (c) 2004 Poul-Henning Kamp <phk@FreeBSD.org>
30 .Nm watchdog
31 .Nd "hardware and software watchdog"
47 .Bl -tag -width "WDIOC_CONTROL int "
49 Pat the watchdog.
51 Enable, disable, or reset the watchdog.
59 of the timeout period for the watchdog.
65 .Xr watchdog 9
68 means that at least one watchdog is armed.
69 By default, this will be a hardware watchdog if one is present, but if
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| /freebsd/sys/dev/ichwd/ |
| H A D | ichwd.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 * Intel ICH Watchdog Timer (WDT) driver
40 * presence of the watchdog timer from the fact that the machine has an
45 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no
52 * For details about the ICH WDT, see Intel Application Note AP-725
53 * (document no. 292273-001). The WDT is also described in the individual
55 * (document no. 252516-001) sections 9.10 and 9.11.
58 * SoC PMC support by Denir Li <denir.li@cas-well.com>
70 #include <sys/watchdog.h>
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| /freebsd/sys/dev/dwwdt/ |
| H A D | dwwdt.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 #include <sys/watchdog.h>
61 #define DWWDT_READ4(sc, reg) bus_read_4((sc)->sc_mem_res, (reg))
63 bus_write_4((sc)->sc_mem_res, (reg), (val))
67 * (pre-restart delay)
88 { "snps,dw-wdt", 1 },
93 "Synopsys Designware watchdog timer");
102 &dwwdt_debug_enabled, 0, "Enable debug mode");
139 device_printf(dev, "Clock: %s\n", clk_get_name(sc->sc_clk)); in dwwdt_debug()
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| /freebsd/sys/powerpc/include/ |
| H A D | spr.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 /* The following routines allow manipulation of the full 64-bit width
88 * architectures the SPR is valid on - 4 for 4xx series,
95 #define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */
96 #define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */
101 #define DSISR_DIRECT 0x80000000 /* Direct-stor
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| /freebsd/sys/contrib/device-tree/src/arm64/mediatek/ |
| H A D | mt7988a.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a73";
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | mediatek,mt7986-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctr
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| H A D | pinctrl-mt7622.txt | 4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 "mediatek,mt7629-pinctrl" for MT7629 SoC
7 - reg: offset and length of the pinctrl space
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells: Should be two. The first cell is the pin number and the
14 - interrupt-controller : Marks the device node as an interrupt controller
16 If the property interrupt-controller is defined, following property is required
17 - reg-names: A string describing the "reg" entries. Must contain "eint".
18 - interrupts : The interrupt output from the controller.
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| H A D | mediatek,mt7981-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctr
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