Home
last modified time | relevance | path

Searched +full:versal +full:- +full:8 (Results 1 – 21 of 21) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@amd.com>
13 The clock controller is a hardware block of Xilinx versal clock tree. It
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
[all …]
H A Dxlnx,clocking-wizard.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0
23 - xlnx,versal-clk-wizard
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]
/linux/drivers/watchdog/
H A Dxilinx_wwdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Window watchdog device driver for Xilinx Versal WWDT
5 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
34 #define XWWDT_ESR_WSW_MASK BIT(8)
51 * struct xwwdt_device - Watchdog device structure
69 struct watchdog_device *xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd; in xilinx_wwdt_start()
74 time_out = xdev->freq * wdd->timeout; in xilinx_wwdt_start()
75 closed_timeout = div_u64(time_out * xdev->close_percent, 100); in xilinx_wwdt_start()
76 open_timeout = time_out - closed_timeout; in xilinx_wwdt_start()
77 wdd->min_hw_heartbeat_ms = xdev->close_percent * 10 * wdd->timeout; in xilinx_wwdt_start()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
/linux/drivers/cdx/controller/
H A Dmc_cdx_pcol.h1 /* SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
19 * 0 7 8 16 20 22 23 24 31
22 * | | \--- Response
23 * | \------- Error
24 * \------------------------------ Resync (always set)
50 #define MCDI_HEADER_DATALEN_LBN 8
51 #define MCDI_HEADER_DATALEN_WIDTH 8
63 #define MCDI_HEADER_XFLAGS_WIDTH 8
76 * - To advance a shared memory request if XFLAGS_EVREQ was set
[all …]
/linux/drivers/edac/
H A DKconfig16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
[all …]
H A Dversal_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Versal memory controller driver
15 #include <linux/firmware/xlnx-zynqmp.h>
16 #include <linux/firmware/xlnx-event-manager.h>
38 #define XDDR_REG_CONFIG0_SIZE_MASK GENMASK(10, 8)
111 #define XDDR_NOC_MATCH_EN_MASK BIT(8)
133 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PCSR_LOCK-XRAM_SLCR-Register
149 * struct ecc_error_info - ECC error log information.
195 * struct ecc_status - ECC status information to report.
209 * struct edac_priv - DDR memory controller private instance data.
[all …]
/linux/drivers/mmc/host/
H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
55 #define PHY_CTRL_OTAPDLY_ENA_MASK BIT(8)
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
[all …]
/linux/drivers/spi/
H A Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
120 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
149 /* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
161 * struct qspi_platform_data - zynqmp qspi platform data structure
169 * struct zynqmp_qspi - Defines qspi driver instance
[all …]
H A Dspi-cadence-quadspi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
30 #include <linux/spi/spi-mem.h>
33 #define CQSPI_NAME "cadence-qspi"
128 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
132 #define CQSPI_STIG_DATA_LEN_MAX 8
[all …]
/linux/drivers/remoteproc/
H A Dxlnx_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
30 (uint32_t)'m' << 8 | (uint32_t)'p')
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
[all …]
/linux/drivers/clk/zynqmp/
H A Dclkc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
19 #include "clk-zynqmp.h"
49 * struct clock_parent - Clock parent
61 * struct zynqmp_clock - Clock
89 #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
141 * zynqmp_is_valid_clock() - Check whether clock is valid or not
149 return -ENODEV; in zynqmp_is_valid_clock()
155 * zynqmp_get_clock_name() - Get name of clock from Clock index
[all …]
/linux/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2021 Xilinx
14 #include <linux/clk-provider.h>
43 #define WZRD_CLKFBOUT_EDGE BIT(8)
50 #define WZRD_EDGE_SHIFT 8
52 #define WZRD_CLKFBOUT_MULT_SHIFT 8
55 #define WZRD_CLKFBOUT_H_SHIFT 8
57 #define WZRD_CLKFBOUT_H_MASK GENMASK(15, 8)
64 #define WZRD_CLKOUT_DIVIDE_WIDTH 8
66 #define WZRD_CLKOUT_FRAC_SHIFT 8
[all …]
/linux/drivers/dma/xilinx/
H A Dzynqmp_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/dma-mapping.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
25 #define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100)
26 #define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104)
27 #define ZYNQMP_DMA_IER (chan->irq_offset + 0x108)
28 #define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10c)
54 #define ZYNQMP_DMA_AXI_RD_DATA BIT(8)
80 #define ZYNQMP_DMA_AWCACHE GENMASK(11, 8)
81 #define ZYNQMP_DMA_AWCACHE_OFST 8
[all …]
/linux/drivers/gpio/
H A Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
64 /* LSW Mask & Data -WO */
[all …]
/linux/drivers/mailbox/
H A Dzynqmp-ipi-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/arm-smccc.h>
17 #include <linux/mailbox/zynqmp-ipi-message.h>
63 #define SRC_BITMASK GENMASK(11, 8)
75 * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
99 * struct zynqmp_ipi_mbox - Description of a ZynqMP IPI mailbox
119 * struct zynqmp_ipi_pdata - Description of z ZynqMP IPI agent platform data.
144 .name = "zynqmp-ipi-mbox",
151 struct zynqmp_ipi_pdata *pdata = ipi_mbox->pdata; in zynqmp_ipi_fw_call()
154 a1 = pdata->local_id; in zynqmp_ipi_fw_call()
[all …]
/linux/drivers/firmware/xilinx/
H A Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
27 #include <linux/firmware/xlnx-zynqmp.h>
28 #include <linux/firmware/xlnx-event-manager.h>
29 #include "zynqmp-debug.h"
36 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
38 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
52 * struct zynqmp_devinfo - Structure for Zynqmp device instance
[all …]
/linux/drivers/net/ethernet/cadence/
H A Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
58 * (bp)->rx_ring_size)
64 * (bp)->tx_ring_size)
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
76 /* Max length of transmit frame must be a multiple of 8 bytes */
77 #define MACB_TX_LEN_ALIGN 8
[all …]
/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]