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/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,versal-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@amd.com>
13 The clock controller is a hardware block of Xilinx versal clock tree. It
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
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/linux/arch/arm64/boot/dts/xilinx/
H A Dversal-net-vn-x-b2197-01-revA.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx Versal Net VNX board revA
6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "versal-net.dtsi"
14 #include "versal-net-clk.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
18 compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net";
19 model = "Xilinx Versal NET VNX revA";
20 dma-coherent;
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dxlnx,versal-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,versal-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 Versal's pin configuration nodes act as a container for an arbitrary number of
21 parameters, such as pull-up, slew rate, etc.
28 const: xlnx,versal-pinctrl
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/linux/drivers/crypto/xilinx/
H A Dxilinx-trng.c1 // SPDX-License-Identifier: GPL-2.0
3 * AMD Versal True Random Number Generator driver
4 * Copyright (c) 2024 - 2025 Advanced Micro Devices, Inc.
11 #include <linux/firmware/xlnx-zynqmp.h>
39 #define TRNG_CTRL_EUMODE_MASK BIT(8)
100 xtrng_readwrite32(rng->rng_base + TRNG_CTRL_OFFSET, TRNG_CTRL_PRNGSRST_MASK, in xtrng_softreset()
103 xtrng_readwrite32(rng->rng_base + TRNG_CTRL_OFFSET, TRNG_CTRL_PRNGSRST_MASK, 0); in xtrng_softreset()
140 byteleft = no_of_random_bytes & (TRNG_SEC_STRENGTH_BYTES - 1); in xtrng_collect_random_data()
142 xtrng_readwrite32(rng->rng_base + TRNG_CTRL_OFFSET, TRNG_CTRL_PRNGSTART_MASK, in xtrng_collect_random_data()
145 ret = xtrng_readblock32(rng->rng_base, (__be32 *)rand_gen_buf, blocks, wait); in xtrng_collect_random_data()
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/linux/drivers/cdx/controller/
H A Dmc_cdx_pcol.h1 /* SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
19 * 0 7 8 16 20 22 23 24 31
22 * | | \--- Response
23 * | \------- Error
24 * \------------------------------ Resync (always set)
50 #define MCDI_HEADER_DATALEN_LBN 8
51 #define MCDI_HEADER_DATALEN_WIDTH 8
63 #define MCDI_HEADER_XFLAGS_WIDTH 8
76 * - To advance a shared memory request if XFLAGS_EVREQ was set
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/linux/drivers/watchdog/
H A Dxilinx_wwdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Window watchdog device driver for Xilinx Versal WWDT
5 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
34 #define XWWDT_ESR_WSW_MASK BIT(8)
57 * struct xwwdt_device - Watchdog device structure
79 struct watchdog_device *xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd; in xilinx_wwdt_start()
82 spin_lock(&xdev->spinlock); in xilinx_wwdt_start()
84 iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET); in xilinx_wwdt_start()
85 iowrite32(~(u32)XWWDT_ESR_WEN_MASK, xdev->base + XWWDT_ESR_OFFSET); in xilinx_wwdt_start()
86 iowrite32((u32)xdev->closed_timeout, xdev->base + XWWDT_FWR_OFFSET); in xilinx_wwdt_start()
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/linux/drivers/edac/
H A Dversalnet_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * AMD Versal NET memory controller driver
57 #define MSG_ERR_OFFSET 8
64 #define NUM_CONTROLLERS 8
74 * struct ecc_error_info - ECC error log information.
122 * struct ecc_status - ECC status information to report.
136 * struct mc_priv - DDR memory controller private instance data.
227 p = &priv->stat; in get_ddr_info()
230 p->channel = 1; in get_ddr_info()
232 p->channel = 0; in get_ddr_info()
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H A Dversal_edac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Versal memory controller driver
15 #include <linux/firmware/xlnx-zynqmp.h>
16 #include <linux/firmware/xlnx-event-manager.h>
38 #define XDDR_REG_CONFIG0_SIZE_MASK GENMASK(10, 8)
111 #define XDDR_NOC_MATCH_EN_MASK BIT(8)
133 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PCSR_LOCK-XRAM_SLCR-Register
149 * struct ecc_error_info - ECC error log information.
195 * struct ecc_status - ECC status information to report.
209 * struct edac_priv - DDR memory controller private instance data.
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/linux/include/linux/firmware/
H A Dxlnx-zynqmp.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2014-2021 Xilinx
6 * Copyright (C) 2022 - 2025 Advanced Micro Devices, Inc.
19 #include <linux/firmware/xlnx-zynqmp-ufs.h>
57 #define PM_VERSAL_FAMILY_CODE 0x2 /* Versal family code */
58 #define PM_VERSAL_NET_FAMILY_CODE 0x3 /* Versal NET family code */
61 #define MODULE_ID_MASK GENMASK(11, 8)
62 #define PLM_MODULE_ID_MASK GENMASK(15, 8)
77 #define SMC_ARG_CNT_64 8U
140 * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error.
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/linux/drivers/spi/
H A Dspi-zynqmp-gqspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
119 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
148 /* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
160 * struct qspi_platform_data - zynqmp qspi platform data structure
168 * struct zynqmp_qspi - Defines qspi driver instance
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/linux/drivers/ufs/host/
H A Dufs-amd-versal2.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/firmware/xlnx-zynqmp.h>
18 #include "ufshcd-dwc.h"
19 #include "ufshcd-pltfrm.h"
20 #include "ufshci-dwc.h"
26 #define MPHY_FW_CALIB_CFG_VAL BIT(8)
58 phy_write_attrs[1].mib_val = (u8)(addr >> 8); in ufs_versal2_phy_reg_write()
60 phy_write_attrs[3].mib_val = (u8)(val >> 8); in ufs_versal2_phy_reg_write()
77 phy_read_attrs[1].mib_val = (u8)(addr >> 8); in ufs_versal2_phy_reg_read()
92 *val |= (mib_val << 8); in ufs_versal2_phy_reg_read()
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/linux/drivers/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
39 called padlock-aes.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
75 to 8 in Coprocessor (CEXxC), EP11 Coprocessor (CEXxP)
87 - A pkey base and API kernel module (pkey.ko) which offers the
89 and the sysfs API and the in-kernel API to the crypto cipher
91 - A pkey pckmo kernel module (pkey-pckmo.ko) which is automatically
94 - A pkey CCA kernel module (pkey-cca.ko) which is automatically
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/linux/drivers/clk/zynqmp/
H A Dclkc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
19 #include "clk-zynqmp.h"
49 * struct clock_parent - Clock parent
61 * struct zynqmp_clock - Clock
89 #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
141 * zynqmp_is_valid_clock() - Check whether clock is valid or not
149 return -ENODEV; in zynqmp_is_valid_clock()
155 * zynqmp_get_clock_name() - Get name of clock from Clock index
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/linux/drivers/firmware/xilinx/
H A Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2025 Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
28 #include <linux/firmware/xlnx-zynqmp.h>
29 #include <linux/firmware/xlnx-event-manager.h>
30 #include "zynqmp-debug.h"
37 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
39 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
54 * struct zynqmp_devinfo - Structure for Zynqmp device instance
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/linux/drivers/remoteproc/
H A Dxlnx_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
30 (uint32_t)'m' << 8 | (uint32_t)'p')
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
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/linux/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2021 Xilinx
14 #include <linux/clk-provider.h>
44 #define WZRD_CLKFBOUT_EDGE BIT(8)
51 #define WZRD_EDGE_SHIFT 8
53 #define WZRD_CLKFBOUT_MULT_SHIFT 8
58 #define WZRD_CLKFBOUT_H_SHIFT 8
60 #define WZRD_CLKFBOUT_H_MASK GENMASK(15, 8)
67 #define WZRD_CLKOUT_DIVIDE_WIDTH 8
69 #define WZRD_CLKOUT_FRAC_SHIFT 8
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/linux/drivers/dma/xilinx/
H A Dzynqmp_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/dma-mapping.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
25 #define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100)
26 #define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104)
27 #define ZYNQMP_DMA_IER (chan->irq_offset + 0x108)
28 #define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10c)
54 #define ZYNQMP_DMA_AXI_RD_DATA BIT(8)
80 #define ZYNQMP_DMA_AWCACHE GENMASK(11, 8)
81 #define ZYNQMP_DMA_AWCACHE_OFST 8
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/linux/drivers/pinctrl/
H A Dpinctrl-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 #include <linux/firmware/xlnx-zynqmp.h>
22 #include <linux/pinctrl/pinconf-generic.h>
28 #include "pinctrl-utils.h"
45 #define DRIVE_STRENGTH_8MA 8
55 * struct zynqmp_pmux_function - a pinmux function
70 * struct zynqmp_pinctrl - driver data
90 * struct zynqmp_pctrl_group - Pin control group info
108 return pctrl->ngroups + zynqmp_desc.npins; in zynqmp_pctrl_get_groups_count()
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