| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | xlnx,versal-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@amd.com>
13 The clock controller is a hardware block of Xilinx versal clock tree. It
20 - enum:
21 - xlnx,versal-clk
22 - xlnx,zynqmp-clk
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| H A D | xlnx,clocking-wizard.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
13 The clocking wizard is a soft ip clocking block of Xilinx versal. It
20 - xlnx,clocking-wizard
21 - xlnx,clocking-wizard-v5.2
22 - xlnx,clocking-wizard-v6.0
23 - xlnx,versal-clk-wizard
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| /linux/arch/arm64/boot/dts/xilinx/ |
| H A D | versal-net-vn-x-b2197-01-revA.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx Versal Net VNX board revA
6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
11 /dts-v1/;
13 #include "versal-net.dtsi"
14 #include "versal-net-clk.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
18 compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net";
19 model = "Xilinx Versal NET VNX revA";
20 dma-coherent;
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| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | arasan,sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | xlnx,versal-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/xlnx,versal-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal Pinctrl
10 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
13 Please refer to pinctrl-bindings.txt in this directory for details of the
17 Versal's pin configuration nodes act as a container for an arbitrary number of
21 parameters, such as pull-up, slew rate, etc.
28 const: xlnx,versal-pinctrl
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| /linux/drivers/cdx/controller/ |
| H A D | mc_cdx_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
19 * 0 7 8 16 20 22 23 24 31
22 * | | \--- Response
23 * | \------- Error
24 * \------------------------------ Resync (always set)
50 #define MCDI_HEADER_DATALEN_LBN 8
51 #define MCDI_HEADER_DATALEN_WIDTH 8
63 #define MCDI_HEADER_XFLAGS_WIDTH 8
76 * - To advance a shared memory request if XFLAGS_EVREQ was set
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| /linux/drivers/watchdog/ |
| H A D | xilinx_wwdt.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Window watchdog device driver for Xilinx Versal WWDT
5 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
34 #define XWWDT_ESR_WSW_MASK BIT(8)
57 * struct xwwdt_device - Watchdog device structure
79 struct watchdog_device *xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd; in xilinx_wwdt_start()
82 spin_lock(&xdev->spinlock); in xilinx_wwdt_start()
84 iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET); in xilinx_wwdt_start()
85 iowrite32(~(u32)XWWDT_ESR_WEN_MASK, xdev->base + XWWDT_ESR_OFFSET); in xilinx_wwdt_start()
86 iowrite32((u32)xdev->closed_timeout, xdev->base + XWWDT_FWR_OFFSET); in xilinx_wwdt_start()
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| /linux/drivers/edac/ |
| H A D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
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| H A D | versalnet_edac.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * AMD Versal NET memory controller driver
57 #define MSG_ERR_OFFSET 8
64 #define NUM_CONTROLLERS 8
74 * struct ecc_error_info - ECC error log information.
122 * struct ecc_status - ECC status information to report.
136 * struct mc_priv - DDR memory controller private instance data.
227 p = &priv->stat; in get_ddr_info()
230 p->channel = 1; in get_ddr_info()
232 p->channel = 0; in get_ddr_info()
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| H A D | versal_edac.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx Versal memory controller driver
15 #include <linux/firmware/xlnx-zynqmp.h>
16 #include <linux/firmware/xlnx-event-manager.h>
38 #define XDDR_REG_CONFIG0_SIZE_MASK GENMASK(10, 8)
111 #define XDDR_NOC_MATCH_EN_MASK BIT(8)
133 * https://docs.xilinx.com/r/en-US/am012-versal-register-reference/PCSR_LOCK-XRAM_SLCR-Register
149 * struct ecc_error_info - ECC error log information.
195 * struct ecc_status - ECC status information to report.
209 * struct edac_priv - DDR memory controller private instance data.
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| /linux/drivers/spi/ |
| H A D | spi-zynqmp-gqspi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
6 * Copyright (C) 2009 - 2015 Xilinx, Inc.
11 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
23 #include <linux/spi/spi-mem.h>
119 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
148 /* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */
160 * struct qspi_platform_data - zynqmp qspi platform data structure
168 * struct zynqmp_qspi - Defines qspi driver instance
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| /linux/drivers/clk/zynqmp/ |
| H A D | clkc.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
12 #include <linux/clk-provider.h>
19 #include "clk-zynqmp.h"
49 * struct clock_parent - Clock parent
61 * struct zynqmp_clock - Clock
89 #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
141 * zynqmp_is_valid_clock() - Check whether clock is valid or not
149 return -ENODEV; in zynqmp_is_valid_clock()
155 * zynqmp_get_clock_name() - Get name of clock from Clock index
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| /linux/drivers/remoteproc/ |
| H A D | xlnx_r5_remoteproc.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
30 (uint32_t)'m' << 8 | (uint32_t)'p')
34 * reflects possible values of xlnx,cluster-mode dt-property
38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
43 * struct mem_bank_data - Memory Bank description
48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
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| /linux/drivers/clk/xilinx/ |
| H A D | clk-xlnx-clock-wizard.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2021 Xilinx
14 #include <linux/clk-provider.h>
44 #define WZRD_CLKFBOUT_EDGE BIT(8)
51 #define WZRD_EDGE_SHIFT 8
53 #define WZRD_CLKFBOUT_MULT_SHIFT 8
58 #define WZRD_CLKFBOUT_H_SHIFT 8
60 #define WZRD_CLKFBOUT_H_MASK GENMASK(15, 8)
67 #define WZRD_CLKOUT_DIVIDE_WIDTH 8
69 #define WZRD_CLKOUT_FRAC_SHIFT 8
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| /linux/drivers/dma/xilinx/ |
| H A D | zynqmp_dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/dma-mapping.h>
19 #include <linux/io-64-nonatomic-lo-hi.h>
25 #define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100)
26 #define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104)
27 #define ZYNQMP_DMA_IER (chan->irq_offset + 0x108)
28 #define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10c)
54 #define ZYNQMP_DMA_AXI_RD_DATA BIT(8)
80 #define ZYNQMP_DMA_AWCACHE GENMASK(11, 8)
81 #define ZYNQMP_DMA_AWCACHE_OFST 8
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| /linux/drivers/gpio/ |
| H A D | gpio-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
64 /* LSW Mask & Data -WO */
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| /linux/drivers/firmware/xilinx/ |
| H A D | zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
28 #include <linux/firmware/xlnx-zynqmp.h>
29 #include <linux/firmware/xlnx-event-manager.h>
30 #include "zynqmp-debug.h"
37 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
39 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
54 * struct zynqmp_devinfo - Structure for Zynqmp device instance
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| /linux/drivers/net/ethernet/cadence/ |
| H A D | macb_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
23 #include <linux/dma-mapping.h>
37 #include <linux/firmware/xlnx-zynqmp.h>
61 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
70 /* Max length of transmit frame must be a multiple of 8 bytes */
71 #define MACB_TX_LEN_ALIGN 8
72 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
88 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
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| /linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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