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/linux/net/netlabel/
H A Dnetlabel_addrlist.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
27 * struct netlbl_af4list - NetLabel IPv4 address list
29 * @mask: IPv4 address mask
30 * @valid: valid flag
35 __be32 mask; member
37 u32 valid; member
42 * struct netlbl_af6list - NetLabel IPv6 address list
44 * @mask: IPv6 address mask
[all …]
H A Dnetlabel_addrlist.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Author: Paul Moore <paul@paul-moore.com>
14 * (c) Copyright Hewlett-Packard Development Company, L.P., 2008
36 * netlbl_af4list_search - Search for a matching IPv4 address entry
52 if (iter->valid && (addr & iter->mask) == iter->addr) in netlbl_af4list_search()
59 * netlbl_af4list_search_exact - Search for an exact IPv4 address entry
61 * @mask: IPv4 address mask
71 __be32 mask, in netlbl_af4list_search_exact() argument
77 if (iter->valid && iter->addr == addr && iter->mask == mask) in netlbl_af4list_search_exact()
86 * netlbl_af6list_search - Search for a matching IPv6 address entry
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,vic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
15 be nested or have the outputs wire-OR'd together.
18 - $ref: /schemas/interrupt-controller.yaml#
23 - arm,pl190-vic
24 - arm,pl192-vic
25 - arm,versatile-vic
[all …]
H A Darm,versatile-fpga-irq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,versatile-fpga-irq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linusw@kernel.org>
20 const: arm,versatile-fpga-irq
22 interrupt-controller: true
24 '#interrupt-cells':
30 clear-mask:
31 description: A mask written to clear all IRQs on the controller at boot.
[all …]
/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_cle.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Applied Micro X-Gene SoC Ethernet Classifier structures
27 if (pdata->enet_id == XGENE_ENET1) { in xgene_cle_idt_to_hw()
41 buf[0] = SET_VAL(CLE_DROP, dbptr->drop); in xgene_cle_dbptr_to_hw()
42 buf[4] = SET_VAL(CLE_FPSEL, dbptr->fpsel) | in xgene_cle_dbptr_to_hw()
43 SET_VAL(CLE_NFPSEL, dbptr->nxtfpsel) | in xgene_cle_dbptr_to_hw()
44 SET_VAL(CLE_DSTQIDL, dbptr->dstqid); in xgene_cle_dbptr_to_hw()
46 buf[5] = SET_VAL(CLE_DSTQIDH, (u32)dbptr->dstqid >> CLE_DSTQIDL_LEN) | in xgene_cle_dbptr_to_hw()
47 SET_VAL(CLE_PRIORITY, dbptr->cle_priority); in xgene_cle_dbptr_to_hw()
55 buf[j++] = SET_VAL(CLE_TYPE, kn->node_type); in xgene_cle_kn_to_hw()
[all …]
/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_flower.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
19 prestera_acl_ruleset_put(template->ruleset); in prestera_flower_template_free()
20 list_del(&template->list); in prestera_flower_template_free()
29 list_for_each_entry_safe(template, tmp, &block->template_list, list) in prestera_flower_template_cleanup()
41 if (act->chain_index <= chain_index) in prestera_flower_parse_goto_action()
43 return -EINVAL; in prestera_flower_parse_goto_action()
45 if (rule->re_arg.jump.valid) in prestera_flower_parse_goto_action()
46 return -EEXIST; in prestera_flower_parse_goto_action()
48 ruleset = prestera_acl_ruleset_get(block->sw->acl, block, in prestera_flower_parse_goto_action()
49 act->chain_index); in prestera_flower_parse_goto_action()
[all …]
/linux/drivers/irqchip/
H A Dirq-versatile-fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * Support for Versatile FPGA-based IRQ controllers
35 * struct fpga_irq_data - irq data container for the FPGA IRQ controller
38 * @valid: mask for valid IRQs on this controller
43 u32 valid; member
55 u32 mask = 1 << d->hwirq; in fpga_irq_mask() local
57 writel(mask, f->base + IRQ_ENABLE_CLEAR); in fpga_irq_mask()
63 u32 mask = 1 << d->hwirq; in fpga_irq_unmask() local
65 writel(mask, f->base + IRQ_ENABLE_SET); in fpga_irq_unmask()
72 seq_puts(p, irq_domain_get_of_node(f->domain)->name); in fpga_irq_print_chip()
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/macsec/
H A Dmacsec_struct.h1 /* SPDX-License-Identifier: GPL-2.0-only */
21 /*! The match mask is per-nibble. 0 means don't care, i.e. every value
68 /*! This is to specify the 40bit SNAP header if the SNAP header's mask
72 /*! This is to specify the 24bit LLC header if the LLC header's mask is
122 /*! Mask is per-byte.
132 * 1: enable comparison of extracted VLAN Valid field.
135 /*! This is bit mask to enable comparison the 8 bit TCI field,
142 /*! Mask is per-byte.
151 /*! Mask is per-byte.
156 /*! Mask is per-byte.
[all …]
/linux/drivers/net/ethernet/pensando/ionic/
H A Dionic_regs.h1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
2 /* Copyright (c) 2018-2019 Pensando Systems, Inc. All rights reserved. */
9 /** struct ionic_intr - interrupt control register set.
11 * @mask: interrupt mask value.
13 * @mask_assert: interrupt mask value on assert.
18 u32 mask; member
28 /** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
30 * @IONIC_INTR_MASK_SET: mask interrupt.
37 /** enum ionic_intr_credits_bits - bitwise composition of credits values.
38 * @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed.
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Ds3c6400.dtsi
H A Ds3c6410.dtsi1 // SPDX-License-Identifier: GPL-2.0
27 valid-mask = <0xffffff7f>;
28 valid-wakeup-mask = <0x00200004>;
32 valid-mask = <0xffffffff>;
33 valid-wakeup-mask = <0x53020000>;
37 clocks: clock-controller@7e00f000 {
38 compatible = "samsung,s3c6410-clock";
40 #clock-cells = <1>;
44 compatible = "samsung,s3c2440-i2c";
46 interrupt-parent = <&vic0>;
[all …]
/linux/drivers/power/reset/
H A Dsyscon-reboot.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 u32 mask; member
21 bool valid; member
46 if (ctx->rd) { in syscon_restart_handle()
47 if (mode < ARRAY_SIZE(ctx->rd->mode_bits) && in syscon_restart_handle()
48 ctx->rd->mode_bits[mode].valid) in syscon_restart_handle()
49 mode_bits = &ctx->rd->mode_bits[mode]; in syscon_restart_handle()
51 mode_bits = &ctx->rd->catchall; in syscon_restart_handle()
53 mode_bits = &ctx->catchall; in syscon_restart_handle()
57 regmap_update_bits(ctx->map, mode_bits->offset, mode_bits->mask, in syscon_restart_handle()
[all …]
/linux/drivers/firmware/imx/
H A Dimx-scu-irq.c1 // SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/firmware/imx/rsrc.h>
40 u32 mask; member
47 u32 mask; member
49 bool valid; member
91 if (scu_irq_wakeup[i].mask) { in imx_scu_irq_work_handler()
92 scu_irq_wakeup[i].valid = false; in imx_scu_irq_work_handler()
105 if (scu_irq_wakeup[i].mask & irq_status) { in imx_scu_irq_work_handler()
106 scu_irq_wakeup[i].valid = true; in imx_scu_irq_work_handler()
107 scu_irq_wakeup[i].wakeup_src = irq_status & scu_irq_wakeup[i].mask; in imx_scu_irq_work_handler()
[all …]
/linux/include/linux/
H A Dregmap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
54 #define REGMAP_UPSHIFT(s) (-(s))
65 * The non-sparse flat cache is provided for compatibility with existing users
66 * and will zero-initialize cache entries for which no defaults are provided.
78 * struct reg_default - Default value for a register.
92 * struct reg_sequence - An individual write from a sequence of writes.
115 * regmap_read_poll_timeout - Pol
1318 regmap_update_bits(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val) regmap_update_bits() argument
1324 regmap_update_bits_async(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val) regmap_update_bits_async() argument
1330 regmap_update_bits_check(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val,bool * change) regmap_update_bits_check() argument
1339 regmap_update_bits_check_async(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val,bool * change) regmap_update_bits_check_async() argument
1347 regmap_write_bits(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val) regmap_write_bits() argument
1489 regmap_field_update_bits(struct regmap_field * field,unsigned int mask,unsigned int val) regmap_field_update_bits() argument
1513 regmap_field_force_update_bits(struct regmap_field * field,unsigned int mask,unsigned int val) regmap_field_force_update_bits() argument
1535 regmap_fields_update_bits(struct regmap_field * field,unsigned int id,unsigned int mask,unsigned int val) regmap_fields_update_bits() argument
1543 regmap_fields_force_update_bits(struct regmap_field * field,unsigned int id,unsigned int mask,unsigned int val) regmap_fields_force_update_bits() argument
1578 unsigned int mask; global() member
1862 regmap_update_bits_base(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val,bool * change,bool async,bool force) regmap_update_bits_base() argument
1898 regmap_field_update_bits_base(struct regmap_field * field,unsigned int mask,unsigned int val,bool * change,bool async,bool force) regmap_field_update_bits_base() argument
1907 regmap_fields_update_bits_base(struct regmap_field * field,unsigned int id,unsigned int mask,unsigned int val,bool * change,bool async,bool force) regmap_fields_update_bits_base() argument
1915 regmap_update_bits(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val) regmap_update_bits() argument
1922 regmap_update_bits_async(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val) regmap_update_bits_async() argument
1929 regmap_update_bits_check(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val,bool * change) regmap_update_bits_check() argument
1938 regmap_update_bits_check_async(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val,bool * change) regmap_update_bits_check_async() argument
1946 regmap_write_bits(struct regmap * map,unsigned int reg,unsigned int mask,unsigned int val) regmap_write_bits() argument
1967 regmap_field_update_bits(struct regmap_field * field,unsigned int mask,unsigned int val) regmap_field_update_bits() argument
1975 regmap_field_force_update_bits(struct regmap_field * field,unsigned int mask,unsigned int val) regmap_field_force_update_bits() argument
2018 regmap_fields_update_bits(struct regmap_field * field,unsigned int id,unsigned int mask,unsigned int val) regmap_fields_update_bits() argument
2026 regmap_fields_force_update_bits(struct regmap_field * field,unsigned int id,unsigned int mask,unsigned int val) regmap_fields_force_update_bits() argument
[all...]
/linux/arch/arm/mach-pxa/
H A Dmfp-pxa2xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/mfp-pxa2xx.c
13 #include <linux/gpio-pxa.h>
21 #include "pxa2xx-regs.h"
22 #include "mfp-pxa2xx.h"
23 #include "mfp-pxa27x.h"
32 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
41 unsigned valid : 1; member
45 unsigned int mask; /* bit mask in PWER or PKWR */ member
46 unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
[all …]
/linux/Documentation/devicetree/bindings/hwmon/
H A Dmax6697.txt4 - compatible:
16 - reg: I2C address
20 - smbus-timeout-disable
23 - extended-range-enable
24 Only valid for MAX6581. Set to enable extended temperature range.
26 - beta-compensation-enable
27 Only valid for MAX6693 and MX6694. Set to enable beta compensation on
30 - alert-mask
31 Alert bit mask. Alert disabled for bits set.
34 - over-temperature-mask
[all …]
/linux/arch/arm/mach-omap2/
H A Dvc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 * struct omap_vc_common - per-VC register/bitfield data
24 * @valid: VALID bitmask in PRM_VC_BYPASS_VAL register
34 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
35 * @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
36 * @i2c_mcode_mask: MCODE field mask for I2C config register
39 * XXX VALID should probably be a shift, not a mask
43 u32 valid; member
63 * struct omap_vc_channel - VC per-instance data
69 * @i2c_high_speed: whether or not to use I2C high-speed mode
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_filter.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
46 static inline bool is_field_set(u32 val, u32 mask) in is_field_set() argument
48 return val || mask; in is_field_set()
51 static inline bool unsupported(u32 conf, u32 conf_mask, u32 val, u32 mask) in unsupported() argument
53 return !(conf & conf_mask) && is_field_set(val, mask); in unsupported()
57 unsigned int ftid, u16 word, u64 mask, u64 val, in set_tcb_field() argument
65 return -ENOMEM; in set_tcb_field()
69 req->reply_ctrl = htons(REPLY_CHAN_V(0) | in set_tcb_field()
[all …]
H A Dcxgb4_tc_u32.c16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 /* Fill ch_filter_specification with parsed match value/mask pair. */
51 __be32 val, mask; in fill_match_fields() local
55 for (i = 0; i < cls->knode.sel->nkeys; i++) { in fill_match_fields()
56 off = cls->knode.sel->keys[i].off; in fill_match_fields()
57 val = cls->knode.sel->keys[i].val; in fill_match_fields()
58 mask = cls->knode.sel->keys[i].mask; in fill_match_fields()
62 if (!cls->knode.sel->keys[i].offmask) in fill_match_fields()
66 if (cls->knode.sel->keys[i].offmask) in fill_match_fields()
[all …]
/linux/rust/kernel/
H A Ddma.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! C header: [`include/linux/dma-mapping.h`](srctree/include/linux/dma-mapping.h)
24 /// Note that this may be `u64` even on 32-bit architectures.
43 unsafe fn dma_set_mask(&self, mask: DmaMask) -> Result { in dma_set_mask()
45 // - By the type invariant of `device::Device`, `self.as_ref().as_raw()` is valid in dma_set_mask()
[all...]
/linux/drivers/memory/
H A Demif.c1 // SPDX-License-Identifier: GPL-2.0-only
33 * struct emif_data - Per device static data for driver's use
38 * to this EMIF - read from MR4 register. If there
44 * @base: base address of memory-mapped IO registers.
48 * frequencies, to avoid re-calculating them on
78 u32 type = emif->plat_data->device_info->type; in do_emif_regdump_show()
79 u32 ip_rev = emif->plat_data->ip_rev; in do_emif_regdump_show()
82 regs->freq/1000000); in do_emif_regdump_show()
84 seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw); in do_emif_regdump_show()
85 seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw); in do_emif_regdump_show()
[all …]
/linux/drivers/clk/ti/
H A Dclkt_dpll.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
17 #include <linux/clk-provider.h>
30 #define DPLL_MULT_UNDERFLOW -1
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
51 #define DPLL_FINT_UNDERFLOW -1
52 #define DPLL_FINT_INVALID -2
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
[all …]
/linux/drivers/ata/
H A Dpata_acpi.c1 // SPDX-License-Identifier: GPL-2.0-only
26 unsigned long mask[2]; member
30 * pacpi_pre_reset - check for 40/80 pin
39 struct ata_port *ap = link->ap; in pacpi_pre_reset()
40 struct pata_acpi *acpi = ap->private_data; in pacpi_pre_reset()
41 if (ACPI_HANDLE(&ap->tdev) == NULL || ata_acpi_gtm(ap, &acpi->gtm) < 0) in pacpi_pre_reset()
42 return -ENODEV; in pacpi_pre_reset()
48 * pacpi_cable_detect - cable type detection
56 struct pata_acpi *acpi = ap->private_data; in pacpi_cable_detect()
58 if ((acpi->mask[0] | acpi->mask[1]) & (0xF8 << ATA_SHIFT_UDMA)) in pacpi_cable_detect()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
H A Ddr_types.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
26 #define mlx5dr_err(dmn, arg...) mlx5_core_err((dmn)->mdev, ##arg)
27 #define mlx5dr_info(dmn, arg...) mlx5_core_info((dmn)->mdev, ##arg)
28 #define mlx5dr_dbg(dmn, arg...) mlx5_core_dbg((dmn)->mdev, ##arg)
94 DR_STE_SIZE_REDUCED = DR_STE_SIZE - DR_STE_SIZE_MASK,
181 /* total number of valid entries belonging to this hash table. This
237 htbl->refcount--; in mlx5dr_htbl_put()
238 if (!htbl->refcount) in mlx5dr_htbl_put()
244 htbl->refcount++; in mlx5dr_htbl_get()
359 ste->refcount--; in mlx5dr_ste_put()
[all …]
/linux/tools/testing/selftests/kvm/lib/arm64/
H A Dgic_v3_its.c1 // SPDX-License-Identifier: GPL-2.0
3 * Guest ITS library, generously donated by drivers/irqchip/irq-gic-v3-its.c
54 return -1; in its_find_baser()
62 baser = ((size / SZ_64K) - 1) | in its_install_table()
76 cbaser = ((size / SZ_4K) - 1) | in its_install_cmdq()
110 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]); in its_fixup_cmd()
111 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]); in its_fixup_cmd()
112 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]); in its_fixup_cmd()
113 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]); in its_fixup_cmd()
118 u64 mask = GENMASK_ULL(h, l); in its_mask_encode() local
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