Lines Matching +full:valid +full:- +full:mask
1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
2 /* Copyright (c) 2018-2019 Pensando Systems, Inc. All rights reserved. */
9 /** struct ionic_intr - interrupt control register set.
11 * @mask: interrupt mask value.
13 * @mask_assert: interrupt mask value on assert.
18 u32 mask; member
28 /** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
30 * @IONIC_INTR_MASK_SET: mask interrupt.
37 /** enum ionic_intr_credits_bits - bitwise composition of credits values.
38 * @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed.
39 * @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit.
60 int intr_idx, u32 mask) in ionic_intr_mask() argument
62 iowrite32(mask, &intr_ctrl[intr_idx].mask); in ionic_intr_mask()
88 int intr_idx, u32 mask) in ionic_intr_mask_assert() argument
90 iowrite32(mask, &intr_ctrl[intr_idx].mask_assert); in ionic_intr_mask_assert()
93 /** enum ionic_dbell_bits - bitwise composition of dbell values.
95 * @IONIC_DBELL_QID_MASK: unshifted mask of valid queue id bits.
99 * @IONIC_DBELL_RING_MASK: unshifted mask of valid ring bits.
108 * @IONIC_DBELL_INDEX_MASK: bit mask of valid index bits, no shift needed.