Lines Matching +full:valid +full:- +full:mask
7 Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
8 Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
15 - reg: Contains 2 offset/length values:
16 - offset and length for the access window.
17 - offset and length for accessing the AEMIF
20 - ti,davinci-chipselect: number of chipselect. Indicates on the
23 Can be in the range [0-3].
27 - ti,davinci-mask-ale: mask for ALE. Needed for executing address
33 - ti,davinci-mask-cle: mask for CLE. Needed for executing command
39 - ti,davinci-mask-chipsel: mask for chipselect address. Needed to mask
42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
43 valid values for davinci driver:
44 - "none"
45 - "soft"
46 - "hw"
48 - ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
50 - nand-bus-width: buswidth 8 or 16. If not present 8.
52 - nand-on-flash-bbt: use flash based bad block table support. OOB
58 - ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
59 valid values for davinci driver:
60 - "none"
61 - "soft"
62 - "hw"
64 - ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8.
66 - ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
70 Nand device bindings may contain additional sub-nodes describing partitions of
73 memory-controller (see Documentation/devicetree/bindings/memory-controllers/
74 davinci-aemif.txt).
79 compatible = "ti,davinci-nand";
82 ti,davinci-chipselect = <1>;
83 ti,davinci-mask-ale = <0>;
84 ti,davinci-mask-cle = <0>;
85 ti,davinci-mask-chipsel = <0>;
86 nand-ecc-mode = "hw";
87 ti,davinci-ecc-bits = <4>;
88 nand-on-flash-bbt;