Lines Matching +full:valid +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0+
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
145 bool valid; member
152 void (*init_supported_interfaces)(unsigned long *mask);
178 return phydev->drv->driver_data; in to_mv3310_chip()
216 temp = chip->hwmon_read_temp_reg(phydev); in mv3310_hwmon_read()
220 *value = ((temp & 0xff) - 75) * 1000; in mv3310_hwmon_read()
225 return -EOPNOTSUPP; in mv3310_hwmon_read()
269 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) in mv3310_hwmon_config()
285 struct device *dev = &phydev->mdio.dev; in mv3310_hwmon_probe()
286 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_hwmon_probe()
289 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); in mv3310_hwmon_probe()
290 if (!priv->hwmon_name) in mv3310_hwmon_probe()
291 return -ENODEV; in mv3310_hwmon_probe()
293 for (i = j = 0; priv->hwmon_name[i]; i++) { in mv3310_hwmon_probe()
294 if (isalnum(priv->hwmon_name[i])) { in mv3310_hwmon_probe()
296 priv->hwmon_name[j] = priv->hwmon_name[i]; in mv3310_hwmon_probe()
300 priv->hwmon_name[j] = '\0'; in mv3310_hwmon_probe()
306 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, in mv3310_hwmon_probe()
307 priv->hwmon_name, phydev, in mv3310_hwmon_probe()
310 return PTR_ERR_OR_ZERO(priv->hwmon_dev); in mv3310_hwmon_probe()
332 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_power_up()
345 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || in mv3310_power_up()
346 priv->firmware_ver < 0x00030000) in mv3310_power_up()
370 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_get_downshift()
373 if (!priv->has_downshift) in mv3310_get_downshift()
374 return -EOPNOTSUPP; in mv3310_get_downshift()
391 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_set_downshift()
395 if (!priv->has_downshift) in mv3310_set_downshift()
396 return -EOPNOTSUPP; in mv3310_set_downshift()
404 * "ethtool --set-phy-tunable ethN downshift on". The intention is in mv3310_set_downshift()
413 return -E2BIG; in mv3310_set_downshift()
415 ds -= 1; in mv3310_set_downshift()
475 return -EINVAL; in mv3310_set_edpd()
493 sfp_parse_support(phydev->sfp_bus, id, support, interfaces); in mv3310_sfp_insert()
494 iface = sfp_select_interface(phydev->sfp_bus, support); in mv3310_sfp_insert()
497 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); in mv3310_sfp_insert()
498 return -EINVAL; in mv3310_sfp_insert()
518 if (!phydev->is_c45 || in mv3310_probe()
519 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) in mv3310_probe()
520 return -ENODEV; in mv3310_probe()
527 dev_warn(&phydev->mdio.dev, in mv3310_probe()
529 return -ENODEV; in mv3310_probe()
532 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in mv3310_probe()
534 return -ENOMEM; in mv3310_probe()
536 dev_set_drvdata(&phydev->mdio.dev, priv); in mv3310_probe()
542 priv->firmware_ver = ret << 16; in mv3310_probe()
548 priv->firmware_ver |= ret; in mv3310_probe()
551 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, in mv3310_probe()
552 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); in mv3310_probe()
554 if (chip->has_downshift) in mv3310_probe()
555 priv->has_downshift = chip->has_downshift(phydev); in mv3310_probe()
566 chip->init_supported_interfaces(priv->supported_interfaces); in mv3310_probe()
596 * the PMA device identifier, with a mask matching models known to have this
601 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) in mv3310_has_pma_ngbaset_quirk()
605 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_has_pma_ngbaset_quirk()
660 return -1; in mv2110_select_mactype()
711 return -1; in mv3310_select_mactype()
716 .valid = true,
721 .valid = true,
725 .valid = true,
729 .valid = true,
737 .valid = true,
741 .valid = true,
746 .valid = true,
751 .valid = true,
755 .valid = true,
759 .valid = true,
763 .valid = true,
768 .valid = true,
776 .valid = true,
780 .valid = true,
784 .valid = true,
789 .valid = true,
793 .valid = true,
797 .valid = true,
802 .valid = true,
810 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_fill_possible_interfaces()
811 unsigned long *possible = phydev->possible_interfaces; in mv3310_fill_possible_interfaces()
812 const struct mv3310_mactype *mactype = priv->mactype; in mv3310_fill_possible_interfaces()
814 if (mactype->interface_10g != PHY_INTERFACE_MODE_NA) in mv3310_fill_possible_interfaces()
815 __set_bit(priv->mactype->interface_10g, possible); in mv3310_fill_possible_interfaces()
817 if (!mactype->fixed_interface) { in mv3310_fill_possible_interfaces()
826 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_config_init()
831 if (!test_bit(phydev->interface, priv->supported_interfaces)) in mv3310_config_init()
832 return -ENODEV; in mv3310_config_init()
834 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in mv3310_config_init()
844 if (!phy_interface_empty(phydev->host_interfaces)) { in mv3310_config_init()
845 mactype = chip->select_mactype(phydev->host_interfaces); in mv3310_config_init()
849 err = chip->set_mactype(phydev, mactype); in mv3310_config_init()
855 mactype = chip->get_mactype(phydev); in mv3310_config_init()
859 if (mactype >= chip->n_mactypes || !chip->mactypes[mactype].valid) { in mv3310_config_init()
861 return -EINVAL; in mv3310_config_init()
864 priv->mactype = &chip->mactypes[mactype]; in mv3310_config_init()
868 /* Enable EDPD mode - saving 600mW */ in mv3310_config_init()
875 if (err && err != -EOPNOTSUPP) in mv3310_config_init()
896 phydev->supported, in mv3310_get_features()
900 phydev->supported, in mv3310_get_features()
912 switch (phydev->mdix_ctrl) { in mv3310_config_mdix()
923 return -EINVAL; in mv3310_config_mdix()
944 if (phydev->autoneg == AUTONEG_DISABLE) in mv3310_config_aneg()
956 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in mv3310_config_aneg()
983 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_update_interface()
985 if (!phydev->link) in mv3310_update_interface()
994 if (priv->mactype->fixed_interface) { in mv3310_update_interface()
995 phydev->interface = priv->mactype->interface_10g; in mv3310_update_interface()
1000 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / in mv3310_update_interface()
1002 * Florian suggests setting phydev->interface to communicate this to the in mv3310_update_interface()
1005 switch (phydev->speed) { in mv3310_update_interface()
1007 phydev->interface = priv->mactype->interface_10g; in mv3310_update_interface()
1010 phydev->interface = PHY_INTERFACE_MODE_5GBASER; in mv3310_update_interface()
1013 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in mv3310_update_interface()
1018 phydev->interface = PHY_INTERFACE_MODE_SGMII; in mv3310_update_interface()
1025 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
1028 phydev->link = 1; in mv3310_read_status_10gbaser()
1029 phydev->speed = SPEED_10000; in mv3310_read_status_10gbaser()
1030 phydev->duplex = DUPLEX_FULL; in mv3310_read_status_10gbaser()
1031 phydev->port = PORT_FIBRE; in mv3310_read_status_10gbaser()
1054 phydev->link = 0; in mv3310_read_status_copper()
1065 phydev->speed = SPEED_10000; in mv3310_read_status_copper()
1069 phydev->speed = SPEED_5000; in mv3310_read_status_copper()
1073 phydev->speed = SPEED_2500; in mv3310_read_status_copper()
1077 phydev->speed = SPEED_1000; in mv3310_read_status_copper()
1081 phydev->speed = SPEED_100; in mv3310_read_status_copper()
1085 phydev->speed = SPEED_10; in mv3310_read_status_copper()
1089 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? in mv3310_read_status_copper()
1091 phydev->port = PORT_TP; in mv3310_read_status_copper()
1092 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? in mv3310_read_status_copper()
1105 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); in mv3310_read_status_copper()
1118 phydev->speed = SPEED_UNKNOWN; in mv3310_read_status()
1119 phydev->duplex = DUPLEX_UNKNOWN; in mv3310_read_status()
1120 linkmode_zero(phydev->lp_advertising); in mv3310_read_status()
1121 phydev->link = 0; in mv3310_read_status()
1122 phydev->pause = 0; in mv3310_read_status()
1123 phydev->asym_pause = 0; in mv3310_read_status()
1124 phydev->mdix = ETH_TP_MDI_INVALID; in mv3310_read_status()
1137 if (phydev->link) in mv3310_read_status()
1146 switch (tuna->id) { in mv3310_get_tunable()
1152 return -EOPNOTSUPP; in mv3310_get_tunable()
1159 switch (tuna->id) { in mv3310_set_tunable()
1165 return -EOPNOTSUPP; in mv3310_set_tunable()
1171 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_has_downshift()
1174 return priv->firmware_ver >= MV_VERSION(0,3,5,0); in mv3310_has_downshift()
1177 static void mv3310_init_supported_interfaces(unsigned long *mask) in mv3310_init_supported_interfaces() argument
1179 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); in mv3310_init_supported_interfaces()
1180 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); in mv3310_init_supported_interfaces()
1181 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); in mv3310_init_supported_interfaces()
1182 __set_bit(PHY_INTERFACE_MODE_XAUI, mask); in mv3310_init_supported_interfaces()
1183 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); in mv3310_init_supported_interfaces()
1184 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); in mv3310_init_supported_interfaces()
1185 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); in mv3310_init_supported_interfaces()
1188 static void mv3340_init_supported_interfaces(unsigned long *mask) in mv3340_init_supported_interfaces() argument
1190 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); in mv3340_init_supported_interfaces()
1191 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); in mv3340_init_supported_interfaces()
1192 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); in mv3340_init_supported_interfaces()
1193 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask); in mv3340_init_supported_interfaces()
1194 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); in mv3340_init_supported_interfaces()
1195 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); in mv3340_init_supported_interfaces()
1198 static void mv2110_init_supported_interfaces(unsigned long *mask) in mv2110_init_supported_interfaces() argument
1200 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); in mv2110_init_supported_interfaces()
1201 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); in mv2110_init_supported_interfaces()
1202 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask); in mv2110_init_supported_interfaces()
1203 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); in mv2110_init_supported_interfaces()
1204 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); in mv2110_init_supported_interfaces()
1207 static void mv2111_init_supported_interfaces(unsigned long *mask) in mv2111_init_supported_interfaces() argument
1209 __set_bit(PHY_INTERFACE_MODE_SGMII, mask); in mv2111_init_supported_interfaces()
1210 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask); in mv2111_init_supported_interfaces()
1211 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask); in mv2111_init_supported_interfaces()
1212 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask); in mv2111_init_supported_interfaces()
1289 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_match_phy_device()
1298 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3340_match_phy_device()
1309 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv211x_match_phy_device()
1335 wol->supported = WAKE_MAGIC; in mv3110_get_wol()
1336 wol->wolopts = 0; in mv3110_get_wol()
1343 wol->wolopts |= WAKE_MAGIC; in mv3110_get_wol()
1351 if (wol->wolopts & WAKE_MAGIC) { in mv3110_set_wol()
1362 ((phydev->attached_dev->dev_addr[5] << 8) | in mv3110_set_wol()
1363 phydev->attached_dev->dev_addr[4])); in mv3110_set_wol()
1369 ((phydev->attached_dev->dev_addr[3] << 8) | in mv3110_set_wol()
1370 phydev->attached_dev->dev_addr[2])); in mv3110_set_wol()
1376 ((phydev->attached_dev->dev_addr[1] << 8) | in mv3110_set_wol()
1377 phydev->attached_dev->dev_addr[0])); in mv3110_set_wol()
1398 /* Reset the clear WOL status bit as it does not self-clear */ in mv3110_set_wol()
1493 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");