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/linux/arch/powerpc/include/asm/
H A Dcpm2.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * All CPM control and status is available through the CPM2 internal
27 /* Device sub-block and page codes.
72 /* CPM2-specific opcodes (see cpm.h for common opcodes)
109 * oversampled clock.
153 * get some microcode patches :-).
154 * The parameter ram space for the SMCs is fifty-some bytes, and
161 /* Define enough so I can at least use the serial port as a UART.
169 uint smc_rstate; /* Internal */
170 uint smc_idp; /* Internal */
[all …]
H A Dcpm1.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * through the MPC8xx internal memory map. See immap.h for details.
11 * are needed. -- Dan
13 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
16 * or other use.
70 /* Define enough so I can at least use the serial port as a UART.
79 uint smc_rstate; /* Internal */
80 uint smc_idp; /* Internal */
81 ushort smc_rbptr; /* Internal */
82 ushort smc_ibc; /* Internal */
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
[all …]
/linux/Documentation/sound/cards/
H A Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
24 use for a lower number of channels is only resource allocation,
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
[all …]
H A Dingenic,adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019-2020 Artur Rojek
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Artur Rojek <contact@artur-rojek.eu>
17 ADC clients must use the format described in
18 https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml,
19 giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
24 - ingenic,jz4725b-adc
25 - ingenic,jz4740-adc
[all …]
/linux/arch/arm/mach-omap2/
H A Domap_hwmod.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2011-2012 Texas Instruments, Inc.
13 * These headers and macros are used to define OMAP on-chip module
16 * omap_hwmod code, in arch/arm/mach-omap2/omap_hwmod.c (as of this
20 * - add interconnect error log structures
21 * - init_conn_id_bit (CONNID_BIT_VECTOR)
22 * - implement default hwmod SMS/SDRC flags?
23 * - move Linux-specific data ("non-ROM data") out
155 * struct omap_hwmod_rst_info - IPs reset lines use by hwmod
[all …]
H A Dmsdi.c1 // SPDX-License-Identifier: GPL-2.0-only
32 /* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
36 * omap_msdi_reset - reset the MSDI IP block
41 * successfully. This is not documented in the TRM. For CLKD, we use
42 * the value that results in the lowest possible clock rate, to attempt
53 /* Enable the MSDI core and internal clock */ in omap_msdi_reset()
59 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) in omap_msdi_reset()
65 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT); in omap_msdi_reset()
68 oh->name, c); in omap_msdi_reset()
70 /* Disable the MSDI internal clock */ in omap_msdi_reset()
/linux/Documentation/devicetree/bindings/sound/
H A Drenesas,fsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas FIFO-buffered Serial Interface (FSI)
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 - $ref: dai-common.yaml#
22 - items:
23 - enum:
24 - renesas,fsi2-sh73a0 # SH-Mobile AG5
25 - renesas,fsi2-r8a7740 # R-Mobile A1
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3528-naneng-combphy
16 - rockchip,rk3562-naneng-combphy
17 - rockchip,rk3568-naneng-combphy
18 - rockchip,rk3576-naneng-combphy
19 - rockchip,rk3588-naneng-combphy
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/linux/include/linux/platform_data/
H A Dad7793.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * enum ad7793_clock_source - AD7793 clock source selection
12 * @AD7793_CLK_SRC_INT: Internal 64 kHz clock, not available at the CLK pin.
13 * @AD7793_CLK_SRC_INT_CO: Internal 64 kHz clock, available at the CLK pin.
14 * @AD7793_CLK_SRC_EXT: Use external clock.
15 * @AD7793_CLK_SRC_EXT_DIV2: Use external clock divided by 2.
25 * enum ad7793_bias_voltage - AD7793 bias voltage selection
27 * @AD7793_BIAS_VOLTAGE_AIN1: Bias voltage connected to AIN1(-).
28 * @AD7793_BIAS_VOLTAGE_AIN2: Bias voltage connected to AIN2(-).
29 * @AD7793_BIAS_VOLTAGE_AIN3: Bias voltage connected to AIN3(-).
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
29 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
30 * @node: &struct device_node for the clock
32 * This clock looks something like this
34 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
35 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
36 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
/linux/include/linux/
H A Dtimekeeper_internal.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * handling code or timekeeping internal code!
15 * timekeeper_ids - IDs for various time keepers in the kernel
25 TIMEKEEPER_AUX_LAST = TIMEKEEPER_AUX_FIRST + MAX_AUX_CLOCKS - 1,
31 * struct tk_read_base - base structure for timekeeping readout
32 * @clock: Current clocksource used for timekeeping.
34 * @cycle_last: @clock cycle value at last update
39 * @base_real: Nanoseconds base value for clock REALTIME readout
47 * @base_real is for the fast NMI safe accessor to allow reading clock
51 struct clocksource *clock; member
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/silabs,si5351.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silicon Labs Si5351A/B/C programmable I2C clock generators
10 The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
12 output clocks are accessible. The internal structure of the clock generators
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
[all …]
H A Dhi6220-clock.txt1 * Hisilicon Hi6220 Clock Controller
3 Clock control registers reside in different Hi6220 system controllers,
11 - compatible: the compatible should be one of the following strings to
12 indicate the clock controller functionality.
14 - "hisilicon,hi6220-acpu-sctrl"
15 - "hisilicon,hi6220-aoctrl"
16 - "hisilicon,hi6220-sysctrl"
17 - "hisilicon,hi6220-mediactrl"
18 - "hisilicon,hi6220-pmctrl"
19 - "hisilicon,hi6220-stub-clk"
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Disil,isl1208.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
11 - Trent Piepho <tpiepho@gmail.com>
20 - isil,isl1208
21 - isil,isl1209
22 - isil,isl1218
23 - isil,isl1219
31 clock-names:
[all …]
/linux/include/uapi/linux/
H A Dcomedi.h1 /* SPDX-License-Identifier: LGPL-2.0+ WITH Linux-syscall-note */
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
24 * don't want this to be much more than you actually use.
32 * NOTE: 'comedi_config --init-data' is deprecated
40 /* length of nth chunk of firmware data -*/
78 /* counters -- these are arbitrary values */
120 /* try to use a real-time interrupt while performing command */
123 /* wake up on end-of-scan events */
166 #define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */
[all …]
/linux/include/soc/at91/
H A Datmel_tcb.h17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
24 * or triggering. Those pins need to be set up for use with the TC block,
30 * timers. Then they use clk_get() and platform_get_irq() to get clock and
37 * struct atmel_tcb_config - SoC data for a Timer/Counter Block
39 * @has_gclk: boolean indicating if a timer counter has a generic clock
50 * struct atmel_tc - information about a Timer/Counter Block
56 * @clk: internal clock source for each of the three channels
[all …]
/linux/sound/pci/echoaudio/
H A Dlayla24_dsp.c3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA.
25 Translation from C++ and adaptation for use in ALSA-Driver
32 static int set_input_clock(struct echoaudio *chip, u16 clock);
44 return -ENODEV; in init_hw()
48 dev_err(chip->card->dev, in init_hw()
49 "init_hw - coul in init_hw()
162 u32 control_reg, clock, base_rate; set_sample_rate() local
252 set_input_clock(struct echoaudio * chip,u16 clock) set_input_clock() argument
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