Lines Matching +full:use +full:- +full:internal +full:- +full:clock

17  * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18  * three general-purpose 16-bit timers.  These timers share one register bank.
19  * Depending on the SOC, each timer may have its own clock and IRQ, or those
23  * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
24  * or triggering.  Those pins need to be set up for use with the TC block,
30  * timers.  Then they use clk_get() and platform_get_irq() to get clock and
37  * struct atmel_tcb_config - SoC data for a Timer/Counter Block
39  * @has_gclk: boolean indicating if a timer counter has a generic clock
50  * struct atmel_tc - information about a Timer/Counter Block
56  * @clk: internal clock source for each of the three channels
57  * @node: list node, for tclib internal use
58  * @allocated: if already used, for tclib internal use
61  * while on others, all TC channels share the same clock and IRQ.
63  * all the entries in @clk may point to the same physical clock.
65  * channel, but they must use IRQF_SHARED in case some of the entries
80 /* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
85  * Two registers have block-wide controls.  These are: configuring the three
98 #define     ATMEL_TC_TC0XC0S	(3 << 0)	/* external clock 0 source */
103 #define     ATMEL_TC_TC1XC1S	(3 << 2)	/* external clock 1 source */
108 #define     ATMEL_TC_TC2XC2S	(3 << 4)	/* external clock 2 source */
118  * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
119  * when it's not "external") is silicon-specific.  AT91 platforms use one
120  * set of definitions; AVR32 platforms use a different set.  Don't hard-wire
121  * such knowledge into your code, use the global "atmel_tc_divisors" ...
122  * where index N is the divisor for clock N+1, else zero to indicate it uses
123  * the 32 KiHz clock.
137 #define     ATMEL_TC_CLKEN	(1 << 0)	/* clock enable */
138 #define     ATMEL_TC_CLKDIS	(1 << 1)	/* clock disable */
144 #define     ATMEL_TC_TCCLKS	(7 << 0)	/* clock source */
153 #define     ATMEL_TC_CLKI	(1 << 3)	/* clock invert */
154 #define     ATMEL_TC_BURST	(3 << 4)	/* clock gating */
247 #define ATMEL_TC_SR	0x20		/* status (read-only) */
248 /* Status-only flags */
249 #define     ATMEL_TC_CLKSTA	(1 << 16)	/* clock enabled */
253 #define ATMEL_TC_IER	0x24		/* interrupt enable (write-only) */
254 #define ATMEL_TC_IDR	0x28		/* interrupt disable (write-only) */
255 #define ATMEL_TC_IMR	0x2c		/* interrupt mask (read-only) */