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/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dxilinx_can.txt2 ---------------------------------------------------------
5 - compatible : Should be:
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
7 - "xlnx,axi-can-1.00.a" for Axi CAN controllers
8 - "xlnx,canfd-1.0" for CAN FD controllers
9 - "xlnx,canfd-2.0" for CAN FD 2.0 controllers
10 - reg : Physical base address and size of the controller
12 - interrupts : Property with a value describing the interrupt
14 - clock-names : List of input clock names
15 - "can_clk", "pclk" (For CANPS),
[all …]
H A Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
31 clock-names:
34 power-domains:
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/freebsd/sys/dev/thunderbolt/
H A Dnhi.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
87 /* 0 = default, 1 = force-on, 2 = force-off */
101 sc->debug = NHI_DEBUG_LEVEL; in nhi_get_tunables()
102 sc->max_ring_count = NHI_DEFAULT_NUM_RINGS; in nhi_get_tunables()
103 sc->force_hcm = NHI_FORCE_HCM; in nhi_get_tunables()
106 val = TB_GET_DEBUG(sc->dev, &sc->debug); in nhi_get_tunables()
110 ufp = devclass_get_device(dc, device_get_unit(sc->dev)); in nhi_get_tunables()
112 TB_GET_DEBUG(ufp, &sc->debug); in nhi_get_tunables()
116 tb_parse_debug(&sc->debug, oid); in nhi_get_tunables()
[all …]
/freebsd/sys/dev/ice/
H A Dice_type.h1 /* SPDX-License-Identifier: BSD-3-Clause */
56 * DIV_S64 - Divide signed 64-bit value with signed 64-bit divisor
60 * Use DIV_S64 for any 64-bit divide which operates on signed 64-bit dividends.
61 * Do not use this for unsigned 64-bi
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H A Dice_iov.c1 /* SPDX-License-Identifier: BSD-3-Clause */
86 * ice_iov_attach - Initialize SR-IOV PF host support
89 * Initialize SR-IOV PF host support at the end of the driver attach process.
94 * - ENOMEM if there is no memory for the PF/VF schemas or iov device
95 * - ENXIO if the device isn't PCI-E or doesn't support the same SR-IOV
97 * - ENOENT if the device doesn't have the SR-IOV capability
102 device_t dev = sc->dev; in ice_iov_attach()
109 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); in ice_iov_attach()
110 pci_iov_schema_add_bool(vf_schema, "mac-anti-spoof", in ice_iov_attach()
112 pci_iov_schema_add_bool(vf_schema, "allow-set-mac", in ice_iov_attach()
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/freebsd/sys/dev/e1000/
H A De1000_regs.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 #define E1000_CTRL 0x00000 /* Device Control - RW */
39 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
40 #define E1000_STATUS 0x00008 /* Device Status - RO */
41 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
42 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
43 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
44 #define E1000_FLA 0x0001C /* Flash Access - RW */
45 #define E1000_MDIC 0x00020 /* MDI Control - RW */
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/freebsd/sys/dev/vnic/
H A Dnic.h46 /* NIC SRIOV VF count */
75 * BGX0-LMAC0-CHAN0 - VNIC CHAN0
76 * BGX0-LMAC1-CHAN0 - VNIC CHAN16
78 * BGX1-LMAC0-CHAN0 - VNIC CHAN128
80 * BGX1-LMAC3-CHAN0 - VNIC CHAN174
87 /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */
93 /* Tx scheduling */
132 /* MSI-X interrupts */
165 * Since both pkt rx and tx notifications are done with same CQ,
281 /* Tx */
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H A Dnic_main.c32 * ----------------------
36 * - PR223573 multicast rx filter
37 * - PR223575 non-promiscuous mode (driver currently forces promisc)
89 /* Structure to be used by the SR-IOV for VF configuration schemas */
116 /* MSI-X */
138 /* PCI SR-IOV interface */
196 nic->dev = dev; in nicpf_attach()
208 nic->node = nic_get_node_id(nic->reg_base); in nicpf_attach()
211 nic->flags &= ~NIC_TNS_ENABLED; in nicpf_attach()
218 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE; in nicpf_attach()
[all …]
H A Dnicvf_queues.c119 #define GET_RBUF_INFO(x) ((struct rbuf_info *)((x) - NICVF_RCV_BUF_ALIGN_BYTES))
129 bit_mask = (1UL << bits) - 1; in nicvf_poll_reg()
138 timeout--; in nicvf_poll_reg()
140 device_printf(nic->dev, "Poll on reg 0x%lx failed\n", reg); in nicvf_poll_reg()
152 *paddr = segs->ds_addr; in nicvf_dmamap_q_cb()
164 bus_get_dma_tag(nic->dev), /* parent tag */ in nicvf_alloc_q_desc_mem()
175 &dmem->dmat); /* dmat */ in nicvf_alloc_q_desc_mem()
178 device_printf(nic->dev, in nicvf_alloc_q_desc_mem()
185 dmem->dmat, /* DMA tag */ in nicvf_alloc_q_desc_mem()
186 &dmem->base, /* virtual address */ in nicvf_alloc_q_desc_mem()
[all …]
/freebsd/sys/dev/aq/
H A Daq_hw_llh.h3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
140 /* get tx dma good octet counter lsw */
143 /* get tx dma good packet counter lsw */
152 /* get tx dma good octet counter msw */
155 /* get tx dma good packet counter msw */
158 /* get rx lro coalesced packet count lsw */
182 /* get msm tx errors counter register */
185 /* get msm tx unicast frames counter register */
188 /* get msm tx multicast frames counter register */
191 /* get msm tx broadcast frames counter register */
[all …]
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dsdio.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2004-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
5 * Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com>
15 /* Mailbox address in SDIO address space */
29 (ATH10K_SDIO_MAX_BUFFER_SIZE - sizeof(struct ath10k_htc_hdr))
36 /* HTC runs over mailbox 0 */
69 /* mode to enable special 4-bit interrupt assertion without clock */
80 * (HTC_HOST_MAX_MSG_PER_RX_BUNDLE) has the HTC header bundle count set
107 /* TODO: remove this and use skb->cb instead, much cleaner approach */
[all …]
H A Dsdio.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2004-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2012,2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com>
37 return __ALIGN_MASK((len), ar_sdio->mbox_info.block_mask); in ath10k_sdio_calc_txrx_padded_len()
47 dev_kfree_skb(pkt->skb); in ath10k_sdio_mbox_free_rx_pkt()
48 pkt->skb = NULL; in ath10k_sdio_mbox_free_rx_pkt()
49 pkt->alloc_len = 0; in ath10k_sdio_mbox_free_rx_pkt()
50 pkt->act_len = 0; in ath10k_sdio_mbox_free_rx_pkt()
51 pkt->trailer_only = false; in ath10k_sdio_mbox_free_rx_pkt()
[all …]
H A Dtargaddrs.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2016 Qualcomm Atheros, Inc.
36 * Pointer to application-defined area, if any.
50 * General-purpose flag bits, similar to SOC_OPTION_* flags.
103 u32 hi_num_bpatch_streams; /* 0x70 -- unused */
124 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
143 /* 0xbc - [31:0]: idle timeout in ms */
150 /* If non-zero, override values sent to Host in WMI_READY event. */
177 /* Interconnect-specific state */
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/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pcireg.h1 /*-
2 * SPDX-License-Identifier: ISC
29 * PCI/PCIe-Gen1 DMA Constants
35 #define BHND_PCIE_DMA32_TRANSLATION 0x80000000 /**< PCIe-Gen1 DMA32 address translation (sb2pcitr…
36 #define BHND_PCIE_DMA32_MASK BHND_PCIE_SBTOPCI2_MASK /**< PCIe-Gen1 DMA32 translation mask */
38 #define BHND_PCIE_DMA64_TRANSLATION _BHND_PCIE_DMA64(TRANSLATION) /**< PCIe-Gen1 DMA64 address tran…
39 #define BHND_PCIE_DMA64_MASK _BHND_PCIE_DMA64(MASK) /**< PCIe-Gen1 DMA64 translation mask */
50 #define BHND_PCI_SBTOPCI_MBOX 0x028 /**< Sonics to PCI mailbox */
76 /* BHND_PCI_ARB_CTL - ParkID (>= rev8) */
98 * (General) PCI/SB mailbox interrupts, two bits per pci function */
[all …]
/freebsd/sys/dev/ixgbe/
H A Dif_ixv.c3 Copyright (c) 2001-2017, Intel Corporation
48 static const char ixv_driver_version[] = "2.0.1-k";
133 /* The MSI-X Interrupt handlers */
251 if_softc_ctx_t scctx = sc->shared; in ixv_if_tx_queues_alloc()
255 MPASS(sc->num_tx_queues == ntxqsets); in ixv_if_tx_queues_alloc()
259 sc->tx_queues = in ixv_if_tx_queues_alloc()
262 if (!sc->tx_queues) { in ixv_if_tx_queues_alloc()
264 "Unable to allocate TX ring memory\n"); in ixv_if_tx_queues_alloc()
268 for (i = 0, que = sc->tx_queues; i < ntxqsets; i++, que++) { in ixv_if_tx_queues_alloc()
269 struct tx_ring *txr = &que->txr; in ixv_if_tx_queues_alloc()
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H A Dixgbe_vf.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 * ixgbe_init_ops_vf - Initialize the pointers for vf
45 * This will assign function pointers, adapter-specific functions can
47 * their own adapter-specific function pointers.
55 hw->mac.ops.init_hw = ixgbe_init_hw_vf; in ixgbe_init_ops_vf()
56 hw->mac.ops.reset_hw = ixgbe_reset_hw_vf; in ixgbe_init_ops_vf()
57 hw->mac.ops.start_hw = ixgbe_start_hw_vf; in ixgbe_init_ops_vf()
59 hw->mac.ops.clear_hw_cntrs = NULL; in ixgbe_init_ops_vf()
60 hw->mac.ops.get_media_type = NULL; in ixgbe_init_ops_vf()
[all …]
/freebsd/sys/dev/qlxge/
H A Dqls_def.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2014 Qlogic Corporation
77 (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
81 #define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22)
106 uint64_t count; member
120 volatile uint32_t txr_free; /* # of free entries in tx ring */
121 volatile uint32_t txr_next; /* # next available tx ring entry */
145 ((QLA_LBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
153 ((QLA_SBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
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/freebsd/sys/dev/cxgbe/common/
H A Dt4_hw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
48 * t4_wait_op_done_val - wait until an operation is completed
51 * @mask: a single-bit field within @reg that indicates completion
60 * operation completes and -EAGAIN otherwise.
73 if (--attempts == 0) in t4_wait_op_done_val()
74 return -EAGAIN; in t4_wait_op_done_val()
88 * t7_wait_sram_done - wait until an operation is completed
99 * operation completes successfully and -EAGAIN if it times out.
114 if (--attempts == 0) in t7_wait_sram_done()
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/freebsd/sys/dev/qlxgbe/
H A Dql_hw.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2016 Qlogic Corporation
45 * Firmware Mailbox Registers
52 * Host Mailbox Registers
203 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
207 bus_write_4((ha->pci_reg), reg, val);\
208 bus_read_4((ha->pci_reg), reg);\
221 * Command Response Interface - Commands
268 * Mailbox Command Response
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dversal-net.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 compatible = "xlnx,versal-net";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&gic>;
21 u-boot {
22 compatible = "u-boot,config";
23 bootscr-address = /bits/ 64 <0x20000000>;
[all …]
/freebsd/sys/dev/mlx4/mlx4_core/
H A Dmlx4_resource_tracker.c17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
226 /* > 0 --> apply mirror when getting into HA mode */
227 /* = 0 --> un-apply mirror when getting out of HA mode */
235 struct rb_node *node = root->rb_node; in res_tracker_lookup()
241 if (res_id < res->res_id) in res_tracker_lookup()
242 node = node->rb_left; in res_tracker_lookup()
243 else if (res_id > res->res_id) in res_tracker_lookup()
244 node = node->rb_right; in res_tracker_lookup()
253 struct rb_node **new = &(root->rb_node), *parent = NULL; in res_tracker_insert()
[all …]
/freebsd/sys/dev/iwm/
H A Dif_iwmreg.h10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
73 * BEGIN iwl-csr.h
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
109 * 31-16: Reserved
110 * 15-
3512 uint8_t count; global() member
3721 struct iwm_statistics_tx tx; global() member
5248 struct iwm_tx_cmd tx; global() member
5916 uint8_t count; global() member
[all...]
/freebsd/sys/contrib/dev/rtw89/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
54 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
111 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
112 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
271 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
272 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
273 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
771 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
977 /* The follow-up are derived from the above. We must ensure that it
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/freebsd/sys/dev/age/
H A Dif_age.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
185 { -1, 0, 0 }
190 { -1, 0, 0 }
195 { -1, 0, 0 }
200 { -1, 0, 0 }
217 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { in age_miibus_readreg()
225 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); in age_miibus_readreg()
247 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { in age_miibus_writereg()
255 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); in age_miibus_writereg()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm8750.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8750-gcc.h>
8 #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interconnect/qcom,icc.h>
12 #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/mailbox/qcom-ipcc.h>
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