Lines Matching +full:tx +full:- +full:mailbox +full:- +full:count

3  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
140 /* get tx dma good octet counter lsw */
143 /* get tx dma good packet counter lsw */
152 /* get tx dma good octet counter msw */
155 /* get tx dma good packet counter msw */
158 /* get  rx lro coalesced packet count lsw */
182 /* get msm tx errors counter register */
185 /* get msm tx unicast frames counter register */
188 /* get msm tx multicast frames counter register */
191 /* get msm tx broadcast frames counter register */
194 /* get msm tx multicast octets counter register 1 */
197 /* get msm tx broadcast octets counter register 1 */
200 /* get msm tx unicast octets counter register 0 */
206 /** \brief Set Tx Register Reset Disable
207 …egisterResetDisable 1 = Disable the S/W reset to MAC-PHY registers, 0 = Enable the S/W reset to MA…
212 /** \brief Get Tx Register Reset Disable
213 *   \return 1 = Disable the S/W reset to MAC-PHY registers, 0 = Enable the S/W reset to MAC-PHY reg…
228 /* set interrupt mapping enable tx */
229 void itr_irq_map_en_tx_set(struct aq_hw *aq_hw, u32 irq_map_en_tx, u32 tx);
234 /* set interrupt mapping tx */
235 void itr_irq_map_tx_set(struct aq_hw *aq_hw, u32 irq_map_tx, u32 tx);
326 /* set rx descriptor write-back interrupt enable */
403 /* set tx dma debug control */
406 /* set tx dma descriptor base address lsw */
411 /* set tx dma descriptor base address msw */
416 /* set tx dma descriptor tail pointer register */
421 /* get tx dma descriptor tail pointer register */
424 /* Set TX Interrupt Moderation Control Register */
477 /* set l2 broadcast count threshold */
518 /* set user-priority tc mapping */
597 /* set  ethertype user-priority enable */
611 /* set ethertype user-priority */
701 /* set  ethertype user-priority enable */
713 /* set ethertype user-priority */
838 /* set tx descriptor enable */
841 /* set tx dca enable */
844 /* set tx dca mode */
847 /* set tx descriptor dca enable */
850 /* get tx descriptor head pointer */
853 /* set tx descriptor length */
857 /* set tx descriptor write-back interrupt enable */
861 /* set tx descriptor write-back threshold */
885 /* set tx buffer enable */
888 /* set tx tc mode */
891 /* set tx buffer high threshold (per tc) */
896 /* set tx buffer low threshold (per tc) */
901 /* set tx dma system loopback enable */
904 /* set tx packet buffer size (per tc) */
911 /* set tx path pad insert enable */
924 /* set tx pkt system loopback enable */
929 /* set tx packet scheduler data arbitration mode */
933 /* set tx packet scheduler descriptor rate current time reset */
937 /* set tx packet scheduler descriptor rate limit */
941 /* set tx packet scheduler descriptor tc arbitration mode */
945 /* set tx packet scheduler descriptor tc max credit */
950 /* set tx packet scheduler descriptor tc weight */
955 /* set tx packet scheduler descriptor vm arbitration mode */
959 /* set tx packet scheduler tc data max credit */
964 /* set tx packet scheduler tc data weight */
969 /* tx */
971 /* set tx register reset disable */
1011 /* get mif up mailbox busy */
1014 /* set mif up mailbox execute operation */
1017 /* get mif uP mailbox address */
1019 /* set mif uP mailbox address */
1022 /* get mif uP mailbox data */
1031 /* clear command for filter l3-l4 */
1048 /* set command for filter l3-l4 */
1101 /* set  ethertype user-priority enable */
1115 /* set ethertype user-priority */