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/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,ucc-hdlc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: High-Level Data Link Control(HDLC)
12 - Frank Li <Frank.Li@nxp.com>
16 const: fsl,ucc-hdlc
24 cell-index:
27 rx-clock-name:
30 - pattern: "^brg([0-9]|1[0-6])$"
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H A Duqe_serial.txt4 compatible : must be "fsl,<chip>-ucc-uart". For t1040, must be
5 "fsl,t1040-ucc-uart".
6 port-number : port number of UCC-UART
7 tx/rx-clock-name : should be "brg1"-"brg16" for internal clock source,
8 should be "clk1"-"clk28" for external clock source.
13 compatible = "fsl,t1040-ucc-uart";
14 port-number = <0>;
15 rx-clock-name = "brg2";
16 tx-clock-name = "brg2";
/linux/sound/soc/intel/boards/
H A Dcht_bsw_rt5645.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht-bsw-rt5645.c - ASoc Machine driver for Intel Cherryview-based platforms
25 #include <sound/soc-acpi.h>
27 #include "../atom/sst-atom-controls.h"
28 #include "../common/soc-intel-quirks.h"
31 #define CHT_CODEC_DAI1 "rt5645-aif1"
32 #define CHT_CODEC_DAI2 "rt5645-aif2"
69 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
70 struct snd_soc_card *card = dapm->card; in platform_clock_control()
80 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); in platform_clock_control()
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H A Dcht_bsw_rt5672.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms
22 #include <sound/soc-acpi.h>
24 #include "../atom/sst-atom-controls.h"
25 #include "../common/soc-intel-quirks.h"
28 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
30 #define CHT_CODEC_DAI "rt5670-aif1"
54 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
55 struct snd_soc_card *card = dapm->card; in platform_clock_control()
62 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); in platform_clock_control()
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.c1 // SPDX-License-Identifier: GPL-2.0
18 /* name, gpio, delay */
19 { TIME_SYNC, { 4, -1 }, { 0, 0 }},
20 { ONE_PPS, { -1, 5 }, { 0, 11 }},
24 /* name, gpio, delay */
29 { TIME_SYNC, { 4, -1 }, { 11, 0 }},
30 { ONE_PPS, { -1, 5 }, { 0, 9 }},
34 /* name, gpio, delay */
39 { ONE_PPS, { -1, 5 }, { 0, 1 }},
50 /* name, gpio, delay */
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Ddavinci-mcasp-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/davinci-mcasp-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jayesh Choudhary <j-choudhary@ti.com>
15 - ti,dm646x-mcasp-audio
16 - ti,da830-mcasp-audio
17 - ti,am33xx-mcasp-audio
18 - ti,dra7-mcasp-audio
19 - ti,omap4-mcasp-audio
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/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DWC HDMI TX Encoder
10 - Mark Yao <markyao0591@gmail.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
18 - $ref: /schemas/sound/dai-common.yaml#
23 - rockchip,rk3228-dw-hdmi
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/linux/Documentation/devicetree/bindings/hsi/
H A Domap-ssi.txt9 - compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
10 - reg-names: Contains the values "sys" and "gdd" (in this order).
11 - reg: Contains a matching register specifier for each entry
12 in reg-names.
13 - interrupt-names: Contains the value "gdd_mpu".
14 - interrupts: Contains matching interrupt information for each entry
15 in interrupt-names.
16 - ranges: Represents the bus address mapping between the main
18 - clock-names: Must include the following entries:
19 "ssi_ssr_fck": The OMAP clock of that name
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8750-qrd.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
20 #include "sm8750-pmics.dtsi"
24 compatible = "qcom,sm8750-qrd", "qcom,sm8750";
25 chassis-type = "handset";
31 wcd939x: audio-codec {
32 compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec";
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc836x_rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2007-2008 MontaVista Software, Inc.
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
[all …]
H A Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
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/linux/drivers/clk/sunxi/
H A Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
29 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
30 * @node: &struct device_node for the clock
32 * This clock looks something like this
34 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
35 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
36 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
[all …]
H A Dmeson-g12b-bananapi-cm4-mnt-reform2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-g12b-bananapi-cm4.dtsi"
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
15 model = "MNT Reform 2 with BPI-CM4 Module";
16 compatible = "mntre,reform2-cm4", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b";
17 chassis-type = "laptop";
25 hdmi_connector: hdmi-connector {
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/linux/sound/soc/fsl/
H A Dfsl_spdif.c1 // SPDX-License-Identifier: GPL-2.0
25 #include "imx-pcm.h"
36 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) argument
51 * @shared_root_clock: flag of sharing a clock source with others;
52 * so the driver shouldn't set root clock rate
56 * @tx_burst: tx maxburst size
58 * @tx_formats: tx supported data format
79 /* IEC958 channel tx status bit */
97 * struct fsl_spdif_priv - Freescale SPDIF private data
111 * @txclk: tx clock sources for playback
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H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
57 #define TX 1 macro
66 * (bit-endianness must match byte-endianness). Processors typically write
68 * written in. So if the host CPU is big-endian, then only big-endian
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/linux/tools/testing/selftests/ptp/
H A Dtestptp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PTP 1588 clock support - User space test program
35 #define CLOCK_INVALID -1
43 static int clock_adjtime(clockid_t id, struct timex *tx) in clock_adjtime() argument
45 return syscall(__NR_clock_adjtime, id, tx); in clock_adjtime()
113 return t->sec * NSEC_PER_SEC + t->nsec; in pctns()
120 " -c query the ptp clock's capabilities\n" in usage()
121 " -d name device to open\n" in usage()
122 " -e val read 'val' external time stamp events\n" in usage()
123 " -E val enable rising (1), falling (2), or both (3) edges\n" in usage()
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/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8569si-pre.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&mpic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
44 bank-width = <1>;
45 device-width = <1>;
[all …]
H A Dt104xd4rdb.dtsi13 * * Neither the name of Freescale Semiconductor nor the
36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
41 bman_fbpr: bman-fbpr {
45 qman_fqd: qman-fqd {
49 qman_pfdr: qman-pfdr {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
[all …]
/linux/drivers/clk/tegra/
H A Dclk-bpmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-2022 NVIDIA Corporation
6 #include <linux/clk-provider.h>
12 #include <soc/tegra/bpmp-abi.h>
22 char name[MRQ_CLK_NAME_MAXLEN]; member
50 } tx; member
68 request.cmd_and_id = (clk->cmd << 24) | clk->id; in tegra_bpmp_clk_transfer()
72 * that contains all possible sub-command structures. Copy the data in tegra_bpmp_clk_transfer()
73 * to that union. Ideally we'd be able to refer to it by name, but in tegra_bpmp_clk_transfer()
77 memcpy(req + 4, clk->tx.data, clk->tx.size); in tegra_bpmp_clk_transfer()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
48 if (display->platform.pantherlake && phy < PHY_C) in intel_encoder_is_c10phy()
51 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy()
74 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
87 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
97 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane), in intel_cx0_program_msgbus_timer()
139 XELPDP_PORT_P2M_MSGBUS_STATUS(display, encoder->port, lane), in intel_clear_response_ready_flag()
146 enum port port = encoder->port; in intel_cx0_bus_reset()
155 drm_err_once(display->drm, in intel_cx0_bus_reset()
168 enum port port = encoder->port; in intel_cx0_wait_for_ack()
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/linux/include/uapi/linux/hdlc/
H A Dioctl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
9 #define CLOCK_EXT 1 /* External TX and RX clock - DTE */
10 #define CLOCK_INT 2 /* Internal TX and RX clock - DCE */
11 #define CLOCK_TXINT 3 /* Internal TX and external RX clock */
12 #define CLOCK_TXFROMRX 4 /* TX clock derived from external RX clock */
27 #define PARITY_CRC16_PR0_CCITT 4 /* CRC16, initial 0x0000, ITU-T version */
28 #define PARITY_CRC16_PR1_CCITT 5 /* CRC16, initial 0xFFFF, ITU-T version */
35 #define LMI_CCITT 3 /* ITU-T Annex A */
42 unsigned int clock_type; /* internal, external, TX-internal etc. */
48 unsigned int clock_type; /* internal, external, TX-internal etc. */
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