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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCRegisterBankInfo.cpp1 //===- PPCRegisterBankInfo.cpp --------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
21 #define DEBUG_TYPE "ppc-reg-bank-info"
31 PPCRegisterBankInfo::PPCRegisterBankInfo(const TargetRegisterInfo &TRI) {} in PPCRegisterBankInfo() argument
64 default: in getRegBankFromRegClass()
73 // Try the default logic for non-generic instructions that are either copies in getInstrMapping()
82 const MachineFunction &MF = *MI.getParent()->getParent(); in getInstrMapping()
85 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); in getInstrMapping() local
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H A DPPCInstructionSelector.cpp1 //===- PPCInstructionSelector.cpp --------------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
28 #define DEBUG_TYPE "ppc-gisel"
71 const PPCRegisterInfo &TRI; member in __anone05d911e0111::PPCInstructionSelector
92 : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), in PPCInstructionSelector()
104 if (RB->getID() == PPC::GPRRegBankID) { in getRegClass()
110 if (RB->getID() == PPC::FPRRegBankID) { in getRegClass()
116 if (RB->getID() == PPC::VECRegBankID) { in getRegClass()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptionRecord.h1 //===- MipsOptionRecord.h - Abstraction for storing information -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // MipsOptionRecord - Abstraction for storing arbitrary information in
14 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
17 //===----------------------------------------------------------------------===//
33 virtual ~MipsOptionRecord() = default;
46 const MCRegisterInfo *TRI = Context.getRegisterInfo(); in MipsRegInfoRecord() local
47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()
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H A DMipsInstructionSelector.cpp1 //===- MipsInstructionSelector.cpp ------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "mips-isel"
62 const MipsRegisterInfo &TRI; member in __anonbf07d5ca0111::MipsInstructionSelector
83 : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), in MipsInstructionSelector()
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-xilinx.txt9 - compatible : Should be "xlnx,xps-gpio-1.00.a"
10 - reg : Address and length of the register set for the device
11 - #gpio-cells : Should be two. The first cell is the pin number and the
13 - gpio-controller : Marks the device node as a GPIO controller.
16 - clocks : Input clock specifier. Refer to common clock bindings.
17 - interrupts : Interrupt mapping for GPIO IRQ.
18 - xlnx,all-inputs : if n-th bit is setup, GPIO-n is input
19 - xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1
20 - xlnx,gpio-width : gpio width
21 - xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode
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H A Dxlnx,gpio-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schema
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86RegisterBankInfo.cpp1 //===- X86RegisterBankInfo.cpp -----------------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
32 X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI) { in X86RegisterBankInfo() argument
41 assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) && in X86RegisterBankInfo()
44 "GPRs should hold up to 64-bit"); in X86RegisterBankInfo()
79 default: in isFPIntrinsic()
97 const TargetRegisterInfo &TRI, in hasFPConstraints() argument
107 // No. Check if we have a copy-like instruction. If we do, then we could in hasFPConstraints()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp1 //===- AArch64RegisterBankInfo.cpp ----------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
47 const TargetRegisterInfo &TRI) { in AArch64RegisterBankInfo() argument
74 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
77 "GPRs should hold up to 128-bit"); in AArch64RegisterBankInfo()
81 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) && in AArch64RegisterBankInfo()
83 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) && in AArch64RegisterBankInfo()
86 "FPRs should hold up to 512-bit via QQQQ sequence"); in AArch64RegisterBankInfo()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBankInfo.cpp1 //===-- RISCVRegisterBankInfo.cpp -------------------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 /// This file implements the targeting of the RegisterBankInfo class for RISC-V.
11 //===----------------------------------------------------------------------===//
29 // clang-format off
39 // clang-format on
119 default: in getRegBankFromRegClass()
163 default: in getFPValueMapping()
181 const TargetRegisterInfo &TRI) const { in hasFPConstraints()
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H A DRISCVInstructionSelector.cpp1 //===-- RISCVInstructionSelector.cpp -----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// RISC-V.
12 //===----------------------------------------------------------------------===//
28 #define DEBUG_TYPE "riscv-isel"
55 // tblgen-erated 'select' implementation, used as the initial selector for
120 const RISCVRegisterInfo &TRI; member in __anon05b3f3090111::RISCVInstructionSelector
124 // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
147 : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), in RISCVInstructionSelector()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp1 //===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls ------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
43 MFMAPaddingRatio("amdgpu-mfma-padding-ratio", cl::init(0), cl::Hidden,
47 //===----------------------------------------------------------------------===//
49 //===----------------------------------------------------------------------===//
60 TRI(TII.getRegisterInfo()), in GCNHazardRecognizer()
61 ClauseUses(TRI.getNumRegUnits()), in GCNHazardRecognizer()
62 ClauseDefs(TRI.getNumRegUnits()) { in GCNHazardRecognizer()
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H A DR600ExpandSpecialInstrs.cpp1 //===- R600ExpandSpecialInstrs.cpp - Expand special instructions ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
25 #define DEBUG_TYPE "r600-expand-special-instrs"
65 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
66 if (OpIdx > -1) { in SetFlagInNewMI()
67 uint64_t Val = OldMI->getOperand(OpIdx).getImm(); in SetFlagInNewMI()
68 TII->setImmOperand(*NewMI, Op, Val); in SetFlagInNewMI()
76 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
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H A DSIMachineFunctionInfo.cpp1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
34 const SITargetLowering *TLI = STI->getTargetLowering(); in getTM()
35 return static_cast<const GCNTargetMachine &>(TLI->getTargetMachine()); in getTM()
90 // Non-entry functions have no special inputs for now, other registers in SIMachineFunctionInfo()
98 if (!F.hasFnAttribute("amdgpu-no-implicitarg-ptr")) in SIMachineFunctionInfo()
114 if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x")) in SIMachineFunctionInfo()
117 if (!F.hasFnAttribute("amdgpu-no-workgroup-id-y")) in SIMachineFunctionInfo()
120 if (!F.hasFnAttribute("amdgpu-no-workgroup-id-z")) in SIMachineFunctionInfo()
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H A DAMDGPUInstructionSelector.cpp1 //===- AMDGPUInstructionSelector.cpp ----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "amdgpu-isel"
46 : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
66 Subtarget->checkSubtargetFeatures(MF.getFunction()); in setupMF()
72 return Def->getOpcode() == AMDGPU::G_AMDGPU_WAVE_ADDRESS in getWaveAddress()
73 ? Def->getOperand(1).getReg() in getWaveAddress()
91 return MRI.getVRegDef(Reg)->getOpcode() != AMDGPU::G_TRUNC && in isVCC()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1 //===- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 // has the FrameSetup/FrameDestroy flag or, alternatively, apply an add-hoc fix
18 //===----------------------------------------------------------------------===//
56 #define DEBUG_TYPE "aarch64-ldst-opt"
59 STATISTIC(NumPostFolded, "Number of post-index updates folded");
60 STATISTIC(NumPreFolded, "Number of pre-index updates folded");
68 DEBUG_COUNTER(RegRenamingCounter, DEBUG_TYPE "-reg-renaming",
72 static cl::opt<unsigned> LdStLimit("aarch64-load-store-scan-limit",
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DPrologEpilogInserter.cpp1 //===- PrologEpilogInserter.cpp - Insert Prolog/Epilog code in function ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
93 /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
100 // MinCSFrameIndex, MaxCSFrameIndex - Keeps the range of callee saved
112 // TRI->requiresFrameIndexScavenging() for the current function.
132 // target-specific addressing mode.
175 /// StackObjSet - A set of stack object indexes
191 if (!MI.isDebugValue() || !MI.getDebugVariable()->isParameter()) in stashEntryDbgValues()
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H A DDetectDeadLanes.cpp1 //===- DetectDeadLanes.cpp - SubRegister Lane Usage Analysis --*- C++ -*---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "detect-dead-lanes"
42 const TargetRegisterInfo *TRI) in DeadLaneDetector() argument
43 : MRI(MRI), TRI(TRI) { in DeadLaneDetector()
44 unsigned NumVirtRegs = MRI->getNumVirtRegs(); in DeadLaneDetector()
51 /// We call this a COPY-like instruction.
79 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); in isCrossCopy() local
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H A DRegisterBankInfo.cpp1 //===- llvm/CodeGen/GlobalISel/RegisterBankInfo.cpp --------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
23 #include "llvm/Config/llvm-config.h"
51 const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1;
53 //------------------------------------------------------------------------------
55 //------------------------------------------------------------------------------
64 assert(RegBanks[Idx]->getID() == Idx && in RegisterBankInfo()
70 bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const { in verify()
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H A DInterferenceCache.h1 //===- InterferenceCache.h - Caching per-block interference ----*- C++ -*--===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // InterferenceCache remembers per-block interference from LiveIntervalUnions,
12 //===----------------------------------------------------------------------===//
33 /// BlockInterference - information about the interference in a single basic
40 BlockInterference() = default;
43 /// Entry - A cache entry containing interference information for all aliases
46 /// PhysReg - The register currently represented.
49 /// Tag - Cache tag is changed when any of the underlying LiveIntervalUnions
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H A DTargetFrameLoweringImpl.cpp1 //===- TargetFrameLoweringImpl.cpp - Implement target frame interface ------==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
30 TargetFrameLowering::~TargetFrameLowering() = default;
41 !MF.getTarget().getMCAsmInfo()->usesWindowsCFI(); in enableCFIFixup()
46 /// (in output arg FrameReg). This is the default implementation which
54 // By default, assume all frame indices are referenced via whatever in getFrameIndexReference()
57 FrameReg = RI->getFrameRegister(MF); in getFrameIndexReference()
59 return StackOffset::getFixed(MFI.getObjectOffset(FI) + MFI.getStackSize() - in getFrameIndexReference()
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H A DRegisterClassInfo.cpp1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // information about target register classes. Callee-saved vs. caller-saved and
14 //===----------------------------------------------------------------------===//
37 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
40 RegisterClassInfo::RegisterClassInfo() = default;
46 auto &STI = MF->getSubtarget(); in runOnMachineFunction()
49 if (STI.getRegisterInfo() != TRI) { in runOnMachineFunction()
50 TRI = STI.getRegisterInfo(); in runOnMachineFunction()
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H A DStackMaps.cpp1 //===- StackMaps.cpp ---------
195 getDwarfRegNum(unsigned Reg,const TargetRegisterInfo * TRI) getDwarfRegNum() argument
211 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo(); parseOperand() local
287 const TargetRegisterInfo *TRI = print() local
370 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo(); parseRegisterLiveOutMask() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp1 //===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "arm-isel"
74 const ARMBaseRegisterInfo &TRI; member in __anone228b8980111::ARMInstructionSelector
79 // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
142 int OpIdx = -1) const;
144 int OpIdx = -1) const;
146 int OpIdx = -1) const;
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveRegUnits.h1 //===- llvm/CodeGen/LiveRegUnits.h - Register Unit Set ----------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
31 const TargetRegisterInfo *TRI = nullptr; variable
36 LiveRegUnits() = default;
39 LiveRegUnits(const TargetRegisterInfo &TRI) { in LiveRegUnits() argument
40 init(TRI); in LiveRegUnits()
50 const TargetRegisterInfo *TRI) { in accumulateUsedDefed() argument
52 if (O->isRegMask()) in accumulateUsedDefed()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp1 //===-- PPCExpandAtomicPseudoInsts.cpp - Expand atomic pseudo instrs. -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
26 #define DEBUG_TYPE "ppc-atomic-expand"
33 const PPCRegisterInfo *TRI; member in __anon356230360111::PPCExpandAtomicPseudo
55 const MCInstrDesc &OR = TII->get(PPC::OR8); in PairedCopy()
56 const MCInstrDesc &XOR = TII->get(PPC::XOR8); in PairedCopy()
76 TRI = &TII->getRegisterInfo(); in runOnMachineFunction()
106 Register DstHi = TRI->getSubReg(Dst, PPC::sub_gp8_x0); in expandMI()
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